DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 4-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe (U.S. PGPub 2006/0138671).
Regarding claim 1, Watanabe teaches a semiconductor package (Fig. 40) comprising: a redistribution substrate including a first surface and a second surface, which are opposite to each other in a first direction (7/12, [0087]-[0088]),
a semiconductor chip mounted on the first surface of the redistribution substrate ([0088], [0073]),
a redistribution pattern in the redistribution substrate and electrically connected to the semiconductor chip ([0090], 10 and portion of layer 9 not under 30),
a metal pattern electrically connected to the redistribution pattern, including a third surface and a fourth surface, which are opposite to each other in the first direction ([0090], 30 and portion of layer 9 under 30); and
a connection terminal on the second surface of the redistribution substrate and being in contact with the fourth surface of the metal pattern (15, [0095]),
wherein at least a portion of the redistribution pattern is in contact with sidewalls of the metal pattern,
wherein the third surface faces the semiconductor chip and is not in contact with the redistribution pattern, and
wherein the fourth surface does not overlap the second surface in the first direction (Fig. 40).
Regarding claim 4, Watanabe teaches wherein the redistribution pattern completely covers the sidewalls and the fourth surface of the metal pattern (Fig. 40).
Regarding claim 5, Watanabe teaches wherein the semiconductor chip includes a chip pad on a lower surface of the semiconductor chip (1/2, 5, [0095]-[0096]),
wherein the redistribution substrate includes a first insulating layer including a trench, such that the chip pad is free of the first insulating layer, and a second insulating layer on the first insulating layer (7, 12, [0094], [0024]), and
wherein the redistribution pattern is disposed in the trench and electrically connected to the chip pad (Fig. 40).
Regarding claim 6, Watanabe teaches wherein the third surface of the metal pattern is in contact with the first insulating layer (Fig. 40, the portion of layer 9 under metal element 30 is interpreted as part of the metal pattern)
Regarding claim 7, Watanabe teaches wherein sidewalls of the semiconductor chip and sidewalls of the redistribution substrate are aligned with each other ([0096]-[0100]).
Regarding claim 8, Watanabe teaches wherein the redistribution substrate is not in contact with the sidewalls and the fourth surface of the metal pattern (Fig. 40).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-3 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (U.S. PGPub 2006/0138671).
Regarding claim 2, Watanabe does not explicitly teach wherein a first distance in the first direction from the first surface to the second surface is less than a second distance in the first direction from the first surface to the fourth surface. Watanabe teaches where the thickness of the metal pattern (corresponding to the distance to the fourth surface) is set such that the redistribution pattern projects from the front surface of the protective layer (corresponding to the second surface) to absorb external stress [0090], [0094], [0099]). Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05(II)A. Applicant cannot argue that the specific claimed distances are critical, as multiple mutually exclusive distances are disclosed (Figs. 3-6). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to modify the teachings of Watanabe such that a first distance in the first direction from the first surface to the second surface is less than a second distance in the first direction from the first surface to the fourth surface for the purpose of optimizing the thickness of the metal pattern to control external stress.
Regarding claim 3, Watanabe does not explicitly teach wherein the second surface and the fourth surface are coplanar. Watanabe teaches where the thickness of the metal pattern (corresponding to the fourth surface) is set such that the redistribution pattern projects from the front surface of the protective layer (corresponding to the second surface) to absorb external stress ([0090], [0094], [0099]). Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05(II)A. Applicant cannot argue that the specific claimed distances are critical, as multiple mutually exclusive distances are disclosed (Figs. 3-6). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to modify the teachings of Watanabe such that the second surface and the fourth surface are coplanar.
Regarding claim 17, Watanabe teaches a semiconductor package (Fig. 40) comprising: a semiconductor chip comprising a chip pad (1/2, 5, [0088], [0073]),
a first insulating layer including a trench, such that the chip pad is free of the first insulating layer, on the semiconductor chip (7, [0030]),
a second insulating layer on the first insulating layer (12, [0098]),
a metal pattern that passes through the second insulating layer and is in contact with the first insulating layer ([0090], 30 and portion of layer 9 under 30),
a redistribution pattern that extends along an upper surface of the first insulating layer, a profile of the metal pattern, and a profile of the trench and is electrically connected to the chip pad ([0090], 10 and portion of layer 9 not under 30), and
a connection terminal, which is electrically connected to the metal pattern (15, [0095]).
Watanabe does not explicitly teach wherein the metal pattern protrudes from an upper surface of the second insulating layer.
Watanabe teaches where the thickness of the metal pattern is set such that the redistribution pattern projects from the upper surface of the second insulating layer layer to absorb external stress ([0090], [0094], [0099]). Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05(II)A. Applicant cannot argue that the specific claimed distances are critical, as multiple mutually exclusive distances are disclosed (Figs. 3-6). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to modify the teachings of Watanabe such that a first distance in the first direction from the first surface to the second surface is less than a second distance in the first direction from the first surface to the fourth surface for the purpose of optimizing the thickness of the metal pattern to control external stress.
Regarding claim 18, Watanabe teaches wherein the metal pattern includes a pattern seed layer and a pattern filling layer on the pattern seed layer, and wherein the pattern seed layer is in contact with the second insulating layer (Fig. 40, 9, 30), wherein the redistribution pattern includes a redistribution seed layer that is in contact with the first insulating layer and the chip pad, and a redistribution filling layer on the redistribution seed layer (9/10, [0092]-[0094]). Watanabe does not explicitly teach in the embodiment of Fig. 40 wherein the redistribution seed layer is in contact with the profile of the metal pattern. Watanabe further teaches wherein the redistribution seed layer is in contact with the profile of a protruding pattern (Figs. 27-29, [0073]-[0076]). Therefore it would have been obvious to a person having ordinary skill in the art to further combine the teachings of Watanabe and Jeong such that the redistribution seed layer is in contact with the profile of the metal pattern for the purpose of providing the seed layer for forming the filling layer (Watanabe, [0032]).
Regarding claim 19, Watanabe teaches wherein the metal pattern does not overlap the second insulating layer in a direction orthogonal to a surface of the second insulating layer (Fig. 40).
Regarding claim 20, Watanabe teaches wherein a width of the first insulating layer and a width of the semiconductor chip are the same as each other (Watanabe, [0096]-[0100]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (U.S. PGPub 2006/0138671) in view of Hsu (U.S. PGPub 2018/0374717).
Regarding claim 9, Watanabe does not explicitly teach wherein a width of the redistribution substrate in a second direction intersecting the first direction is greater than a width of the semiconductor chip in the second direction.
Hsu teaches wherein a width of a redistribution substrate connected to a semiconductor chip is greater than a width of the semiconductor chip in a horizontal direction (Fig. 18, 200, 330, [0024]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Hsu with Watanabe such that a width of the redistribution substrate in a second direction intersecting the first direction is greater than a width of the semiconductor chip in the second direction for the purpose of forming a fan-out package (Hsu, [0001]).
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (U.S. PGPub 2006/0138671) in view of Jeong (U.S. PGPub 2017/0125369).
Regarding claim 10, Watanabe teaches a semiconductor package (Fig. 40) comprising:
a redistribution substrate including a first insulating layer and a second insulating layer, which are stacked in a first direction, the redistribution substrate including a first surface and a second surface, which are opposite to each other in the first direction (12/7, [0087]-[0088]),
a redistribution pattern in the redistribution substrate ([0090], 10 and portion of layer 9 not under 30),
a metal pattern at least partially in the first insulating layer and electrically connected to the redistribution pattern ([0090], 30 and portion of layer 9 under 30); and
a connection terminal on the first surface of the redistribution substrate, having one end electrically connected to the metal pattern, (15, [0095]),
wherein at least a portion of the redistribution pattern is in contact with sidewalls of the metal pattern (Fig. 40),
wherein the metal pattern is not in contact with the first surface,
wherein a portion of the redistribution pattern overlaps the first insulating layer in a second direction crossing the first direction, and another portion of the redistribution pattern is on the first insulating layer, and
wherein a portion of the metal pattern is in contact with the second insulating layer (Fig. 40).
Watanabe does not explicitly teach a semiconductor chip mounted on the first surface of the redistribution substrate, the connection terminal having the other end electrically connected to the semiconductor chip.
Jeong teaches wherein a redistribution substrate is connected to a semiconductor chip on one surface and to another semiconductor chip via a connection terminal on the other surface (Fig. 2, 212/112, 162, 120/130, [0038]-[0055]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Jeong with Watanabe such that a semiconductor chip is mounted on the first surface of the redistribution substrate, the connection terminal having the other end electrically connected to the semiconductor chip for the purpose of providing a chip-to-chip stacked package (Jeong, [0004]).
Regarding claim 11, the combination of Watanabe and Jeong does not explicitly teach wherein at least a portion of the metal pattern protrudes from the first surface. Watanabe teaches where the thickness of the metal pattern is set such that the redistribution pattern projects from the front surface of the protective layer (corresponding to the first surface) to absorb external stress (Watanabe, [0090], [0094], [0099]). Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05(II)A. Applicant cannot argue that the specific claimed distances are critical, as multiple mutually exclusive distances are disclosed (Figs. 3-6). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to modify the teachings of Watanabe such that wherein at least a portion of the metal pattern protrudes from the first surface for the purpose of optimizing the thickness of the metal pattern to control external stress.
Regarding claim 12, the combination of Watanabe and Jeong teaches wherein the metal pattern includes a pattern seed layer and a pattern filling layer on the pattern seed layer, and wherein the pattern seed layer is in contact with the second insulating layer (Watanabe, Fig. 40, 9, 30). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Watanabe and Jeong for the reasons set forth in the rejection of claim 10.
Regarding claim 13, the combination of Watanabe and Jeong teaches wherein the redistribution pattern includes a redistribution seed layer and a redistribution filling layer on the redistribution seed layer (Watanabe, 9/10, [0092]-[0094]). Watanabe further teaches wherein the redistribution seed layer extends along the sidewalls and upper surface of a protruding pattern (Figs. 27-29, [0073]-[0076]). Therefore it would have been obvious to a person having ordinary skill in the art to further combine the teachings of Watanabe and Jeong such that the redistribution seed layer extends along the sidewalls and an upper surface of the metal pattern for the purpose of providing the seed layer for forming the filling layer (Watanabe, [0032]).
Regarding claim 14, the combination of Watanabe and Jeong teaches wherein a width of the redistribution substrate in the second direction is the same as a width of the semiconductor chip in the second direction. (Watanabe, [0096]-[0100]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Watanabe and Jeong for the reasons set forth in the rejection of claim 10.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (U.S. PGPub 2006/0138671) in view of Jeong (U.S. PGPub 2017/0125369) and Hsu (U.S. PGPub 2018/0374717).
Regarding claim 15, the combination of Watanabe and Jeong does not explicitly teach wherein at least a portion of the first surface of the redistribution substrate does not overlap the semiconductor chip in the first direction.
Hsu teaches wherein a width of a redistribution substrate connected to a semiconductor chip is greater than a width of the semiconductor chip in a horizontal direction (Fig. 18, 200, 330, [0024]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Hsu with Watanabe and Jeong such that at least a portion of the first surface of the redistribution substrate does not overlap the semiconductor chip in the first direction for the purpose of forming a fan-out package (Hsu, [0001]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (U.S. PGPub 2006/0138671) in view of Jeong (U.S. PGPub 2017/0125369) and Paek (U.S. Pat. 8618658).
Regarding claim 16, the combination of Watanabe and Jeong does not explicitly teach wherein the first insulating layer at least partially covers a portion of an upper surface of the metal pattern.
Paek teaches a redistribution laver over a projection in an insulating layer, a connection terminal over the projection, wherein the insulating layer at least partially covers a portion of an upper surface of the projection (Fig. 4, 130, 120, 140, 460, col. 5, l. 20-50).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Paek with Watanabe and Jeong such that the first insulating layer at least partially covers a portion of an upper surface of the metal pattern for the purpose of reducing material costs and reducing pitch (Paek, col. 5, l. 39-50).
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812
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