Prosecution Insights
Last updated: August 17, 2026
Application No. 18/739,666

REPAIR STRUCTURE FOR BONDED SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Jun 11, 2024
Examiner
MCCUTCHEON, COLIN RUSSELL
Art Unit
Tech Center
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
46 granted / 53 resolved
+26.8% vs TC avg
Strong +22% interview lift
Without
With
+21.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
17 currently pending
Career history
71
Total Applications
across all art units

Statute-Specific Performance

§103
65.5%
+25.5% vs TC avg
§102
27.7%
-12.3% vs TC avg
§112
6.8%
-33.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 53 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) was submitted on 6/11/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 and 8-9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu et al (US 2025/0293222 A1, hereafter Yu). Re Claim 1, Yu discloses a semiconductor device (FIG. 4; [0038]-[0045]), comprising: a first semiconductor structure (101, 209; [0018]) bonded to a second semiconductor structure (313; [0031]); a plurality of metal pads (207, 323; [0029]) at an interface portion (209, 321; [0025], [0032]) between the first semiconductor structure (101, 209) and the second semiconductor structure (313; [0032]); and a structure (401; [0038]) disposed around the plurality of metal pads (207, 323; [0038]), wherein the structure (401) comprises a plurality of chemical agents (“initiators and/or catalysts”; [0041]). Re Claim 8, Yu discloses the device according to Claim 1, while further disclosing wherein the first semiconductor structure (101, 209) is hybrid bonded to the second semiconductor structure (313; [0035]). Re Claim 9, Yu discloses the device according to Claim 1, while further disclosing wherein the plurality of metal pads (207, 323) are disposed in a dielectric layer (211, 325; [0027], [0032]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-7 and 10-16 are rejected under 35 U.S.C. 103 as being unpatentable over Raravikar et al (US 2008/0237822 A1, hereafter Raravikar) in view of Parsons et al (US 6,319,757 B1, hereafter Parsons). Re Claim 1, Raravikar discloses a semiconductor device (FIG. 2, with reference to FIG. 4; [0018]-[0021]), comprising: a first structure (202; [0018]) bonded to a second semiconductor structure (204; [0018], [0002] for material); a plurality of metal pads (224; [0018]) at an interface portion (portion containing 224, 216, 226; [0018]) between the first structure (202) and the second semiconductor structure (204; [0018]); and a structure (210; [0018]) disposed around the plurality of metal pads (224; [0018]), wherein the structure (210) comprises a plurality of chemical agents (216, 218; [0021]). Raravikar does not explicitly disclose wherein the first structure (202) is a semiconductor structure. Parsons teaches a semiconductor device (FIG. 1; column 8, lines 54-59) wherein the first structure (30; column 8, line 58) is a semiconductor structure (column 8, line 58). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Raravikar with the limitations taught by Parsons to use AlN as the material for the package substrate as a functionally equivalent material substitution yielding the predictable result of a semiconductor substrate with a sufficient degree of electrical isolation as taught by Parsons (column 4, lines 66-67). Re Claim 2, Raravikar and Parsons teach the device according to Claim 1, while Raravikar further teaches wherein the plurality of chemical agents (216, 218) comprise a plurality of healing agents (218; [0021]) in a resin matrix (“polymer matrix”; [0021]). Re Claim 3, Raravikar and Parsons teach the device according to Claim 2, while Raravikar further teaches wherein the resin matrix (“polymer matrix”) includes a plurality of catalysts (216; [0021]), and wherein the plurality of catalysts (216) are structured to polymerize the plurality of healing agents (218; [0021]) upon contacting the plurality of healing agents (218; [0021]). Re Claim 4, Raravikar and Parsons teach the device according to Claim 3, while Raravikar further teaches wherein one or more of the plurality of catalysts (216) comprise a Grubbs catalyst ([0021]). Re Claim 5, Raravikar and Parsons teach the device according to Claim 3, while Raravikar further teaches wherein upon propagation of a crack (221; [0022]) adjacent the polymerized plurality of healing agents (218), the polymerized plurality of healing agents (218) are structured to seal the crack (221) and prevent further propagation of the crack (221; [0022]). Re Claim 6, Raravikar and Parsons teach the device according to Claim 2, while Raravikar further teaches wherein the plurality of healing agents (218) are in respective ones of a plurality of capsules ([0021]). Re Claim 7, Raravikar and Parsons teach the device according to Claim 2, while Raravikar further teaches wherein the plurality of healing agents (218) are in a plurality of channels (respective space between metal pads 224; [0018]). Re Claim 10, Raravikar and Parsons teach the device according to Claim 1, while Raravikar further teaches wherein the structure (210) comprises a plurality of respective portions (210, portions on either sides of 224; [0018]) spaced apart from each other ([0018]) and corresponding to respective ones of the plurality of metal pads (224; [0018]). Re Claim 11, Raravikar and Parsons teach the device according to Claim 1, while Raravikar further teaches wherein the semiconductor device comprises at least one dielectric layer (207; [0018], see [0004] for epoxy material) disposed around the plurality of metal pads (224; [0018]), wherein the structure (210) is disposed over and under the at least one dielectric layer (207; [0018], at least a bottom portion of 210 at a lower elevation/under the topmost portion of 207). Re Claim 12, Raravikar discloses a semiconductor device (FIG. 2, with reference to FIG. 4; [0018]-[0021]), comprising: a first structure (202, 226; [0018]) comprising a first plurality of metal pads (226; [0018]); a second semiconductor structure (204, 224; [0018], [0002] for material) comprising a second plurality of metal pads (224; [0018]); wherein the first structure (202, 226) is bonded to the second semiconductor structure (204, 224; [0018]); wherein respective ones of the first plurality of metal pads (226) are aligned with respective ones of the second plurality of metal pads (224; [0018]); and a repair structure (210; [0018]-[0021]) disposed around the respective ones of the first plurality of metal pads (226) and the second plurality of metal pads (224; [0018], in close proximity to). Raravikar does not explicitly disclose wherein the first structure (202) is a semiconductor structure. Parsons teaches a semiconductor device (FIG. 1; column 8, lines 54-59) wherein the first structure (30; column 8, line 58) is a semiconductor structure (column 8, line 58). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Raravikar with the limitations taught by Parsons to use AlN as the material for the package substrate as a functionally equivalent material substitution yielding the predictable result of a semiconductor substrate with a sufficient degree of electrical isolation as taught by Parsons (column 4, lines 66-67). Re Claim 13, Raravikar and Parsons teach the device according to Claim 12, while Raravikar further teaches wherein the repair structure (210) comprise a plurality of healing agents (218; [0021]). Re Claim 14, Raravikar and Parsons teach the device according to Claim 13, while Raravikar further teaches wherein the plurality of healing agents (218) are in respective ones of a plurality of capsules ([0021]). Re Claim 15, Raravikar and Parsons teach the device according to Claim 13, while Raravikar further teaches wherein the plurality of healing agents (218) are in a plurality of channels (respective space between metal pads 224; [0018]). Re Claim 16, Raravikar and Parsons teach the device according to Claim 13, while Raravikar further teaches wherein the repair structure (210) further comprises a plurality of catalysts (216; [0021]), and wherein the plurality of catalysts (216) are structured to polymerize the plurality of healing agents (218) upon contacting the plurality of healing agents (218; [0021]). Claim 17 rejected under 35 U.S.C. 103 as being unpatentable over Raravikar and Parsons, as applied to Claim 12, further in view of Cheng et al (US 2025/0210484 A1, hereafter Cheng). Re Claim 17, Raravikar and Parsons teach the device according to Claim 12, but they do not explicitly disclose wherein the first semiconductor structure (202, 226) is hybrid bonded to the second semiconductor structure (204, 224). However, Cheng teaches a semiconductor device (FIG. 10; [0150]) comprising metal pads (30; [0150]) for a package substrate (110; [0150]) embedded in a dielectric layer (11a; [0150]). Together in combination, Raravikar, Parsons, and Cheng now teach that the first semiconductor structure (202, 226) is hybrid bonded to the second semiconductor structure (204, 224) by the definition provided in lines 2-4 of [0023] of the instant specification. Specifically, metal pads (Raravikar: 224, 226) are embedded in the dielectric layer 210 of Raravikar and the dielectric layer 11a of Cheng, respectively, at a bond interface (see FIG. Z1 below) on each semiconductor structure (Raravikar: 204, 202). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device according to Claim 12 with the limitations taught by Cheng to utilize a dielectric layer (Cheng: 11a) around the package substrate’s metal pads (Raravikar: 226) to facilitate isolation of electrical connection (thereby teaching the first and second semiconductor structures of Raravikar are hybrid bonded, as described above) as taught by Cheng ([0150]). PNG media_image1.png 195 442 media_image1.png Greyscale FIG. Z1: Annotated version of FIG. 2 of Raravikar Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lefevre et al (US 2024/0170444 A1, hereafter Lefevre). Re Claim 18, Lefevre discloses in a first embodiment a semiconductor device (FIG. 9B; [0065]), comprising: two or more semiconductor dies (200; [0039]) hybrid bonded together ([0068]); a plurality of metal structures (206; [0046]) at an interface portion (304, interface between previously vertically separated 206 portions; [0067]) between a first semiconductor die (200, bottom portion in FIG. 9B; [0065]) of the two or more semiconductor dies (200) and a second semiconductor die (200, top portion in FIG. 9B; [0065]) of the two or more semiconductor dies (200; [0067]); and a structure (209; [0050]) disposed around respective ones of the plurality of metal structures (206; [0050]). Lefevre does not explicitly disclose in the first embodiment wherein the structure (209) comprises a plurality of chemical agents. However, Lefevre teaches in a second embodiment (FIG. 10; [0054]-[0058]) wherein the structure (404; [0056]) comprises a plurality of chemical agents (405; [0056]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by the first embodiment of Lefevre with the limitations taught by the second embodiment of Lefevre to have a plurality of chemical agents (Lefevre: 405) within the structure (Lefevre: 209) to allow for the ring-opening reaction to occur at lower temperatures as taught by Lefevre ([0056]). Allowable Subject Matter Claims 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Re Claim 19, the prior art cannot anticipate, or render obvious, the limitations of: the plurality of chemical agents comprise a plurality of healing agents in a resin matrix, in combination with the additionally claimed features of Claim 19. Claim 20 is objected to due to being dependent on objected Claim 19. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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Prosecution Timeline

Jun 11, 2024
Application Filed
Aug 06, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+21.9%)
3y 3m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 53 resolved cases by this examiner. Grant probability derived from career allowance rate.

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