DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15 in the “RESPONSE TO RESTRICTION REQUIREMENT” filed on September 3, 2026 is acknowledged. Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions in Groups II and III.
Information Disclosure Statement
The references listed in the Information Disclosure Statement (IDS) submitted on June 11, 2024 have been considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, lines 4-5 recite: “a second chip comprising core circuits and peripheral circuits configured to control operation of the memory cells”. This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention may be ascertained. No new matter may be added. For example, it is unclear what core circuits are versus peripheral circuits. As another example, it is unclear what the components are of the core circuits and what the components are of the peripheral circuits. As an additional example, it is unclear whether both the core circuits and the peripheral circuits control operation of the memory cells or just the peripheral circuits control operation of the memory cells. As a further example, it is unclear how the core circuits and peripheral circuits are configured to control operation of the memory cells. That is, what is the structure of the core circuits and/or the peripheral circuits that controls operation of the memory cells? For purpose of examination, the Examiner is interpreting lines 4-5 of claim 1 as reciting: “a second chip which controls operation of the memory cells” because of these ambiguities.
Claims 2-15 are also rejected under 35 U.S.C. 112(b) because the depend, directly or indirectly, from claim 1.
Regarding claim 14, lines 3-5 recite “wherein first ones of the peripheral circuits are configured to decode commands and second ones of the peripheral circuits are configured to control an input and/or output of address and data.” This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention may be ascertained. No new matter may be added. For example, it is unclear how the first ones of the peripheral circuits are configured to decode commands. That is, what is the structure of the first ones of the peripheral circuits that decodes commands? As another example, it is unclear how the second ones of the peripheral circuits are configured to control an input and/or output of address and data. That is, what is the structure of the second ones of the peripheral circuits that controls an input and/or output of address and data? For purpose of examination, the Examiner is interpreting lines 3-5 of claim 14 as not reciting: “wherein first ones of the peripheral circuits and second ones of the peripheral circuits” because of these ambiguities. Claim 15 is additionally rejected under 35 U.S.C. 112(b) because of its dependency on claim 14.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0130430 A1 (Im) in view of US 6,097,244 (Chen).
Regarding claim 1, Im discloses, A semiconductor memory device comprising:
a first chip (annotated FIG. 3, below) comprising a cell region (annotated FIG. 3, below) that includes memory cells (memory cells (220); FIG. 3; [0029]) and a dummy region (annotated FIG. 3, below) that includes a dummy cell (dummy cell (222); FIG. 3; [0029])1; and
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a second chip (annotated FIG. 3, above) comprising core circuits and peripheral circuits configured to control operation of the memory cells (220),2 and 3 the second chip (annotated FIG. 3, above) overlapping at least a part of the first chip (annotated FIG. 3, above) along a vertical direction (annotated FIG. 3, above),
wherein the dummy region (annotated FIG. 3, above) of the first chip (annotated FIG. 3, above) comprises at least one variable resistor (variable resistor (216); FIG. 3; [[0039]) that includes the dummy cell (222).
But, Im does not appear to explicitly disclose,
a dummy region that includes a set of dummy cell transistors; and
wherein the at least one variable resistor includes the set of dummy cell transistors.
However, in analogous art, Chen discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that transistors may be predicably utilized as variable resistors in the linear region of operation thereof (Col. 3, lines 13-16).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Im and Chen before him/her that it was common knowledge that the dummy region (annotated FIG. 3, above) of Im includes a set of dummy cell (222); FIG. 3; [0029]) transistors, as taught by Chen, by operating these transistors in their linear range, as also taught by Chen, thereby making these transistors structurally the variable resistance devices disclosed by Im. Please see, MPEP 2144(I)—Rational May Be In a Reference, OR Reasoned From Common Knowledge In The Art, Scientific Principles, Art-Recognized Equivalents, Or Legal Precedent.
Regarding claim 13, Im in view of Chen discloses, The semiconductor memory device of claim 1, wherein the first chip (annotated FIG. 3, above) and the second chip (annotated FIG. 3, above) are electrically connected to each other by first bonding metals (first bonding metals (200); FIG. 3; [0029]) in a lower portion of the first chip (annotated FIG. 3, above) and second bonding metals (bonding metals (130e); FIG. 3; [0033]) in an upper portion of the second chip (annotated FIG. 3, above).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Im in view of Chen and further in view of US 2014/0001527 A1 (Myung).
Regarding claim 2, Im in view of Chen does not appear to explicitly disclose, wherein the set of dummy cell transistors comprise vertical channel transistors.
However, in analogous art, Myung discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that vertical channel transistors have an improved degree of integration and improved operational characteristics, and accordingly, may be applied to memory cells of memory devices ([0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Im, Chen, and Myung before him/her that the set of dummy cell (222) transistors of Im in view of Chen comprise vertical channel transistors, as taught by Myung, to improve both the degree of integration and the operation operational characteristics in the memory device of Im in view Chen, as also taught by Myung. Please see, MPEP 2143(G)--Some Teaching, Suggestion, or Motivation in the Prior Art That Would Have Led One of Ordinary Skill To Modify the Prior Art Reference or To Combine Prior Art Reference Teachings To Arrive at the Claimed Invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Im in view of Chen and Myung, and further in view of US 2013/0320433 A1 (Cho).
Regarding claim 3, Im in view of Chen and Myung does not appear to explicitly disclose, wherein the vertical channel transistors comprises first gate electrodes on a first side of a channel layer, and second gate electrodes on a second side of the channel layer.
However, in analogous art, Cho discloses that it was well known to one of ordinary skill in the art before the effective filing date of the claimed invention that a vertical channel transistor (FIG. 1A) may be predicably fabricated to include a first gate electrode (first gate electrode (29); FIG. 1A; [0038]) on a first side (annotated FIG. 1A., below) of a channel layer (channel layer (26); FIG. 1A; [0039]) and a second gate electrode (second gate electrode (36); FIG. 1A; [0038]) on a second side (annotated FIG. 1A, below) of the channel layer (26).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Im, Chen, Myung, and Cho before him/her that the vertical channel transistors of Im in view of Chen and Myung can be predicably fabricated to include first gate electrodes on a first side of a channel layer, and second gate electrodes on a second side of the channel layer, as taught by Cho, with no change in the function of the vertical channel transistors of Im in view of Chen and Myung because they would still operate a dummy cell transistors. Please see, MPEP 2143(A)—Combining Prior Art Elements According To Known Methods To Yield Predicable Results.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Im in view of Chen and further in view of US 11,482,262 B1 (Lee).
Regarding claim 7, Im in view of Chen discloses, The semiconductor memory device of claim 1, wherein the at least one variable resistor (216) comprises a plurality of variable resistors (plurality of variable resistors (216); annotated FIG. 3, above; [0039]), and
wherein the voltage divider is configured to generate at least one intermediate voltage based on a ratio of respective resistance values of the plurality of variable resistors (216) included in the voltage divider.4
But, Im in view of Chen does not appear to explicitly disclose, wherein the dummy region of the first chip comprises a voltage divider comprising the plurality of variable resistors electrically connected in series.
However, in analogous art, Lee discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a voltage divider (voltage divider (1202; FIG. 14; Col. 16, line 32) may include resistors connected in series (Col. 19, lines 57-59).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Im, Chen, and Lee before him/her that the plurality of variable resistors (216) of the dummy region (annotated FIG. 3, above) of the first chip (annotated FIG. 3, above) of Im in view of Chen, may be predicably electrically connected in series to create a voltage divider, as taught by Lee, with no change in the function of variable resistors (216) because they still operate as variable resistance devices. Please see, MPEP 2143(A), above.
Regarding claim 8, Im in view of Chen and further in view of Lee discloses, The semiconductor memory device of claim 7, wherein at least one of the peripheral circuits of the second chip (annotated FIG. 3, above) operates based on the at least one intermediate voltage as a reference voltage.5
Allowable Subject Matter
Claims 4-6, 9-12, 14, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if both: (i) the rejections thereof under 35 U.S.C. 112(b) are overcome and (ii) they are rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an Examiner’s Statement of Reasons for Allowance.
Regarding claim 4, Im in view of Chen and Myung, and further in view of Cho does not appear to explicitly disclose, in combination with the other recited elements and limitations of claims 1-3 from which claim 4 depends,
wherein the at least one variable resistor comprises a set of variable resistors, each variable resistor of the set of variable resistors including a subset of dummy cell transistors, among the set of dummy cell transistors, electrically connected in series with one another, and
wherein the first gate electrodes and the second gate electrodes of the subset of dummy cell transistors included in the set of variable resistors correspond to a first gate line and a second gate line, respectively.
Regarding claims 5 and 6, they depend, directly or indirectly, from claim 4 and are, therefore, objected to because they include all the limitations of claim 4.
Regarding claim 9, the combination of Im in view of Chen discloses, wherein the at least one variable resistor (216) comprises a third variable resistor (annotated FIG. 3, above) and a fourth variable resistor (annotated FIG. 3, above), the semiconductor memory device further comprising: . . . an amplifier (amplifier (1420); FIG. 1; [0020]). However, Im in view of Chen does not appear to explicitly disclose, in combination with the other recited elements and limitations of claim 1 from which claim 9 depends, the semiconductor memory device further comprising:
a low-dropout (LDO) regulator comprising the third variable resistor and the fourth variable resistor connected in series and a pass transistor,
wherein the dummy region of the first chip comprises the third variable resistor and the fourth variable resistor of the LDO regulator, and
wherein the second chip comprises the amplifier and the pass transistor of the LDO regulator.
Regarding claims 10-12, they depend, directly or indirectly, from claim 9 and are, therefore, objected to because they include all the limitations of claim 9.
Regarding claim 14, Im in view of Chen discloses, a bitline sense amplifier (bitline sense amplifier (1420); FIG. 1; [0020]). However, Im in view of Chen does not appear to explicitly disclose, in combination with the other recited elements and limitations of claim 1 from which claim 14 depends,
wherein the core circuits comprise a sub-wordline driver and a bitline sense amplifier, and
wherein first ones of the peripheral circuits are configured to decode commands and second ones of the peripheral circuits are configured to control an input and/or output of address and data.6
Regarding claim 15, it depends from claim 14 and is, therefore, objected to because it includes all the limitations of claim 15.
Any comments considered necessary by Applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0305268 A1 (Sato)—Discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor memory device may include first and second vertically overlapping chips (FIG. 4). Also discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor memory device includes amplifiers (21), decoders (19 and 20), and controllers (12) (FIG. 1).
US 2011/0267864 A1 (Suzuki)—Discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor memory device may include multiple vertically overlapping chips having memory cells ((NC0-NC3); FIG. 5) thereon. Also discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor memory device may include first and second circuits ((IDC and CCO); FIG. 5) on a chip.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 The Examiner notes that Im does disclose that dummy cell (222) includes a variable resistor (216); FIG. 3; [[0039] which may be a variable resistance device ([0040]).
2 Please see the rejection of claim 1 under 35 U.S.C. 112(b), above, for how this recited language of claim 1 is being interpreted for purpose of examination.
3 The Examiner respectfully submits that the recited limitation of “core circuits and peripheral circuits configured to control operation of the memory cells” is a manner of operating the semiconductor memory device that does not distinguish claim 1 from the prior art. Please see, MPEP 2114(II)—Manner Of Operating The Device Does Not Differentiate Apparatus Claim From The Prior Art.
4 The Examiner respectfully submits that the recited limitation of “wherein the voltage divider is configured to generate at least one intermediate voltage based on a ratio of respective resistance values of the plurality of variable resistors included in the voltage divider” is a manner of operating the voltage divider that does not distinguish claim 7 from the prior art. Please see, MPEP 2114(II), above.
5 The Examiner respectfully submits that the recited limitation of “wherein at least one of the peripheral circuits of the second chip operates based on the at least one intermediate voltage as a reference voltage” is a manner of operating at least one of the second chip that does not distinguish claim 8 from the prior art. Please see, MPEP 2114(II), above.
6 Please see the rejection of claim 14 under 35 U.S.C. 112(b), above, for how this recited language of claim 14 is being interpreted for purpose of examination.
