DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on June 11, 2024 has been considered by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on July 25, 2024.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: NITRIDE SEMICONDUCTOR DEVICE INCLUDING AN END GROOVE PORTION PROVIDING IMPROVED OFF PROPERTIES.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Tsurumi (US 2022/0344518 A1) in view of Okita (US 2016/0118491 A1), and further in view of Ueno (US 2015/0021618 A1).
Claim 1, Tsurumi discloses a nitride semiconductor device (nitride semiconductor device 100A, [0144], Fig. 9) comprising:
a substrate (substrate 12, [0057], Fig. 9);
a first nitride semiconductor layer (drift layer 14 is a first nitride semiconductor layer, hereinafter, first nitride semiconductor layer 14, [0057], Fig. 9) disposed above the substrate 12 (first nitride semiconductor layer 14 is disposed above the substrate 12, [0057], Fig. 9);
a first high-resistance semiconductor layer (high-resistance layer 16 is a first high-resistance layer, hereinafter, first high-resistance layer 16, [0057], Fig. 9) that is disposed above the first nitride semiconductor layer 14 (first high-resistance layer 16 is disposed above the first nitride semiconductor layer 14, [0057], Fig. 9) and has a resistance higher than a resistance of the first nitride semiconductor layer 14 (first high-resistance layer 16 has a resistance higher than a resistance of the first nitride semiconductor layer 14, [0061], Fig. 9);
a first p-type nitride semiconductor layer (first base layer 18 is a first p-type nitride semiconductor layer, hereinafter, first p-type nitride semiconductor layer 18, [0064], Fig. 9) disposed above the first high-resistance semiconductor layer 16 (first p-type nitride semiconductor layer 18 is disposed above the first high-resistance semiconductor layer 16, [0064], Fig. 9);
a second high-resistance semiconductor layer (high-resistance layer 116 is a second high-resistance semiconductor layer, hereinafter, second high-resistance semiconductor layer 116, [0107], Fig. 9) that is disposed above the first p-type nitride semiconductor layer 18 (second high-resistance semiconductor layer 116 is disposed above the first p-type nitride semiconductor layer 18, [0107], Fig. 9) and has a resistance higher than the resistance of the first nitride semiconductor layer 18 (second high-resistance semiconductor layer 116 has a resistance higher than the resistance of the first nitride semiconductor layer 18, [0107], Fig. 9);
an electron mobility layer (electron transport layer 24 is an electron mobility layer, hereinafter, electron mobility layer 24, [0067], Fig. 9) and an electron supply layer (electron supply layer 26, [0069], Fig. 9) disposed sequentially from a lower side to cover a first opening (gate opening 22 is a first opening, hereinafter, first opening 22, [0109], Fig. 9) and a top surface of the second high-resistance semiconductor layer 116, the first opening penetrating through the second high-resistance semiconductor layer 116, the first p-type nitride semiconductor layer 18, and the first high-resistance semiconductor layer 16 (electron mobility layer 24 and electron supply layer 26 are disposed sequentially from a lower side to cover a first opening and a top surface of the second high-resistance semiconductor layer 116, the first opening 22 penetrating through the second high-resistance semiconductor layer 116, the first p-type nitride semiconductor layer 18, and the first high-resistance semiconductor layer 16, [0069], Fig. 9) and reaching the first nitride semiconductor layer 14 (electron mobility layer 24 and electron supply layer 26 are disposed sequentially and directly in contact with the first nitride semiconductor layer 14, [0069], Fig. 9);
a gate electrode (gate electrode 38, [0072], Fig. 9) disposed above the electron supply layer 26 to cover the first opening 22 (gate electrode 38 is disposed above the electron supply layer 26 to cover the first opening 22, [0072], Fig. 9);
a source electrode (source electrode 32, [0072], Fig. 9) that is spaced from the gate electrode 38 and is in contact with the electron supply layer 26 (source electrode 32 is spaced from the gate electrode 38 and is in contact with the electron supply layer 26, [0072], Fig. 9);
a potential-fixing electrode (potential fixing electrode 36, [0075], Fig. 9) that is disposed in contact with the first p-type nitride semiconductor layer 18 (potential fixing electrode 36 is disposed in contact with the first p-type nitride semiconductor layer 18, [0075], Fig. 9) and is connected to the source electrode 32 in a second opening (source opening 30 is a second opening, hereinafter, second opening 30, [0070], Fig. 9) that penetrates through the second high-resistance semiconductor layer 116 and reaches the first p-type nitride semiconductor layer 18 (potential fixing electrode 36 is connected to the source electrode 32 in a second opening 30 that penetrates through the second high-resistance semiconductor layer 116 and reaches the first p-type nitride semiconductor layer 18, [0075], Fig. 9);
a drain electrode (drain electrode 40, [0079], Fig. 9) disposed below the substrate 12 (drain electrode 40 is disposed below the substrate 12, [0079], Fig. 9).
Tsurumi does not explicitly disclose an insulating film that covers the gate electrode and the source electrode, wherein the insulating film is further disposed along an inner surface of a groove portion that is disposed in an end portion of the nitride semiconductor device, and penetrates through the first p-type nitride semiconductor layer and reaches the first high-resistance semiconductor layer; and the first high-resistance semiconductor layer is a high-resistance AlGaN layer.
However, Okita discloses the first high-resistance semiconductor layer (superlattice (SL) layer 91 is a first high-resistance semiconductor layer, hereinafter, first high-resistance semiconductor layer 91; Tsurumi, first high-resistance layer 16, [0057], Fig. 9) is a high-resistance AlGaN layer (first high-resistance semiconductor layer 91 is a high-resistance AlGaN layer, [0061], Fig. 5; Tsurumi, first high-resistance layer 16, [0057], Fig. 9). The combination to utilize AlGaN as a high-resistance layer in a nitride semiconductor device improves the vertical withstand voltage between ohmic electrodes (Okita, [0061]).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date to utilize AlGaN as a high-resistance layer in a nitride semiconductor device to improve the vertical withstand voltage between ohmic electrodes (Okita, [0061]).
Tsurumi/Okita does not explicitly disclose an insulating film that covers the gate electrode and the source electrode, wherein the insulating film is further disposed along an inner surface of a groove portion that is disposed in an end portion of the nitride semiconductor device, and penetrates through the first p-type nitride semiconductor layer and reaches the first high-resistance semiconductor layer.
However, Ueno discloses an insulating film that covers the gate electrode and the source electrode (Ueno, protective film 180 is an insulating film, hereinafter, insulating film 180 and covers gate electrode 196 and source electrode 192 (i.e. x-direction), [0035], Fig. 5; Tsurumi, source electrode 32 and gate electrode 38, [0072], Fig. 9; Okita, first high-resistance semiconductor layer 91, [0059], Fig. 5), wherein the insulating film is further disposed along an inner surface of a groove portion that is disposed in an end portion of the nitride semiconductor device (Ueno, insulating film 180 is further disposed along an inner surface of a groove portion that is disposed in an end portion of the nitride semiconductor device 14, [0035], Fig. 5; Tsurumi, nitride semiconductor device 100A, [0144], Fig. 9; Okita, first high-resistance semiconductor layer 91, [0059], Fig. 5), and penetrates through the first p-type nitride semiconductor layer and reaches the first high-resistance semiconductor layer (Ueno, insulating film 180 penetrates through the first p-type nitride semiconductor layer 130 and reaches the first high-resistance semiconductor layer 120, [0035], Fig. 5; Tsurumi, first p-type nitride semiconductor layer 18 is disposed above the first high-resistance semiconductor layer 16, [0064], Fig. 9; Okita, first high-resistance semiconductor layer 91, [0059], Fig. 5). The utilization of an insulating film in combination with the nitride semiconductor device allows for improvement of the electrical properties and workability of the protective film as a final encapsulation step (Ueno, [0008]).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date to utilize an insulating film in combination with the nitride semiconductor device allows for improvement of the electrical properties and workability of the protective film as a final encapsulation step (Ueno, [0008]).
Claim 4, Tsurumi/Okita/Ueno discloses the nitride semiconductor device (Tsurumi, nitride semiconductor device 100A, [0144], Fig. 9; Okita, nitride semiconductor device, [0058], Fig. 5; Ueno, nitride semiconductor device 14, [0061], Fig. 5) according to claim 1.
Tsurumi/Okita/Ueno discloses wherein the insulating film contains at least Si and N (Ueno, insulating film 180 contains Si and N (i.e. SiN), [0083], Fig. 5; Tsurumi, source electrode 32 and gate electrode 38, [0072], Fig. 9; Okita, first high-resistance semiconductor layer 91, [0059], Fig. 5).
Claim 5, Tsurumi/Okita/Ueno discloses the nitride semiconductor device (Tsurumi, nitride semiconductor device 100A, [0144], Fig. 9; Okita, nitride semiconductor device, [0058], Fig. 5; Ueno, nitride semiconductor device 14, [0061], Fig. 5) according to claim 1.
Tsurumi/Okita/Ueno discloses comprising: a second p-type nitride semiconductor layer disposed between the gate electrode and the electron supply layer (Tsurumi, threshold adjustment layer 28 is a second p-type nitride semiconductor layer, hereinafter, second p-type nitride semiconductor layer 28 and is disposed between the gate electrode 38 and the electron supply layer 26, [0072], Fig. 9; Okita, nitride semiconductor device, [0058], Fig. 5; Ueno, nitride semiconductor device 14, [0061], Fig. 5).
Claim 6, Tsurumi/Okita/Ueno discloses the nitride semiconductor device (Tsurumi, nitride semiconductor device 100A, [0144], Fig. 9; Okita, nitride semiconductor device, [0058], Fig. 5; Ueno, nitride semiconductor device 14, [0061], Fig. 5) according to claim 1.
Tsurumi/Okita/Ueno discloses comprising: a field plate disposed above the insulating film to project to the groove portion (Ueno, field plate electrode 193 is a field plate, hereinafter, field plate 193 and is disposed above the insulating film 180 to protect the groove portion, [0061], Fig. 5; Tsurumi, nitride semiconductor device 100A, [0144], Fig. 9; Okita, nitride semiconductor device, [0058], Fig. 5).
Claim 7, Tsurumi/Okita/Ueno discloses the nitride semiconductor device (Tsurumi, nitride semiconductor device 100A, [0144], Fig. 9; Okita, nitride semiconductor device, [0058], Fig. 5; Ueno, nitride semiconductor device 14, [0061], Fig. 5) according to claim 6.
Tsurumi/Okita/Ueno discloses wherein the field plate is electrically connected to the source electrode (Ueno, field plate 193 is electrically connected to the source electrode 192, [0061], Fig. 5; Tsurumi, nitride semiconductor device 100A, [0144], Fig. 9; Okita, nitride semiconductor device, [0058], Fig. 5).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Tsurumi in view of Okita in view of Ueno, and further in view of Ujita (US 2021/0005742 A1).
Claim 2, Tsurumi/Okita/Ueno discloses the nitride semiconductor device (Tsurumi, nitride semiconductor device 100A, [0144], Fig. 9; Okita, semiconductor device is a nitride semiconductor device, hereinafter, nitride semiconductor device, [0058], Fig. 5; Ueno, semiconductor device 14 is a nitride semiconductor device, hereinafter, nitride semiconductor device 14, [0061], Fig. 5) according to claim 1.
Tsurumi/Okita/Ueno does not explicitly disclose comprising: a second nitride semiconductor layer disposed between the first nitride semiconductor layer and the first high-resistance semiconductor layer, wherein the second nitride semiconductor layer is an undoped AlGaN layer.
However, Ujita discloses comprising: a second nitride semiconductor layer disposed between the first nitride semiconductor layer and the first high-resistance semiconductor layer (Ujita, first base layer 16 is a second nitride semiconductor layer, hereinafter, second nitride semiconductor layer 16 and is disposed between the drift layer 14 which is the first nitride semiconductor layer, hereinafter, first nitride semiconductor layer 14 and the first high-resistance semiconductor layer, [0072], Fig. 12; Tsurumi, first high-resistance layer 16 is disposed above the first nitride semiconductor layer 14, [0057], Fig. 9; Okita, nitride semiconductor device, [0058], Fig. 5; Ueno, nitride semiconductor device 14, [0061], Fig. 5),
wherein the second nitride semiconductor layer is an undoped AlGaN layer (Ujita, second nitride semiconductor layer 16 may be an undoped AlGaN layer similarly to third base layer 20 and electron supply layer 26, [0083], Fig. 12; Tsurumi, first high-resistance layer 16 is disposed above the first nitride semiconductor layer 14, [0057], Fig. 9; Okita, nitride semiconductor device, [0058], Fig. 5; Ueno, nitride semiconductor device 14, [0061], Fig. 5). The combination to utilize an additional undoped AlGaN nitride semiconductor layer in combination with above lying and under lying nitride and high-resistance layers enables formation of a two-dimensional electron gas within the electron mobility layer (Ujita, [0082]).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date to utilize an additional undoped AlGaN nitride semiconductor layer in combination with above lying and under lying nitride and high-resistance layers to enable formation of a two-dimensional electron gas within the electron mobility layer (Ujita, [0082]).
Claim 3, Tsurumi/Okita/Ueno/Ujita discloses the nitride semiconductor device (Tsurumi, nitride semiconductor device 100A, [0144], Fig. 9; Okita, nitride semiconductor device, [0058], Fig. 5; Ueno, nitride semiconductor device 14, [0061], Fig. 5; Ujita, Fig. 12) according to claim 2.
Tsurumi/Okita/Ueno/Ujita discloses wherein the high-resistance AlGaN layer has a resistance higher than a resistance of the undoped AlGaN layer (Ujita, high-resistance AlGaN layer has a resistance higher than a resistance of the undoped AlGaN layer, [0072], Fig. 12; Tsurumi, high-resistance AlGaN layer has a resistance higher than a resistance of the undoped AlGaN layer, [0057], Fig. 9; Okita, nitride semiconductor device, [0058], Fig. 5; Ueno, nitride semiconductor device 14, [0061], Fig. 5).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ogawa (US 2023/0047842 A1) discloses in [0055], Fig. 6, a nitride semiconductor device 210 further including nitride and high-resistance nitride layers in combination with a gate electrode 32, source electrode 36, and drain electrode 38.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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