Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/11/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Objections
Claim 3 is objected to because of the following informalities:
Claim 3 lacks a period in front of the number “3”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin US 20150364394 A1 in view of Yu et al US 20200075496 A1. Yu et al will be referenced to as Yu henceforth.
Regarding Claim 1,
Lin teaches:
“A method of manufacturing a semiconductor package, comprising: disposing a semiconductor chip (semiconductor die 124, [0049], FIG. 3b) and a molding layer (encapsulant 198, [0058], FIG. 3c) covering the semiconductor chip on a carrier substrate (carrier 190, [0078], FIG. 3c);removing the carrier substrate to expose a surface of the semiconductor chip (surface 200, [101], FIG. 3D);”
Lin doesn’t substantially teach:
“forming a first insulating layer on the surface of the semiconductor chip, the first insulating layer having a first opening;forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer;forming a second insulating layer on the first insulating layer to cover the first redistribution pattern; andperforming a planarization process on the second insulating layer to expose the first redistribution pattern.”
However, Yu teaches:
“forming a first insulating layer on the surface of the semiconductor chip (Yu: first dielectric material 106, [0020], FIG. 9C), the first insulating layer having a first opening (Yu: via openings 105, [0092], FIG. 9A);forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer (Yu: conductive material 221, [0095], FIG. 9F);forming a second insulating layer on the first insulating layer to cover the first redistribution pattern (Yu: second dielectric material 108 , [0099] FIG. 9I); andperforming a planarization process on the second insulating layer to expose the first redistribution pattern (Yu: [0099], FIG. 9J).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lin is modifiable in view of Yu by incorporating the method of forming an RDL structure of Yu into Lin.
This is because the method of forming an RDL structure of Yu provides good planarity for to-be-formed upper layers for a low cost (Yu: [0036]).
Regarding Claim 2,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 1, wherein the performing of the planarization process comprises: removing the second insulating layer disposed on the first redistribution pattern to expose a surface of the first redistribution pattern (Yu: [0099], FIG. 9J); and planarizing the exposed surface of the first redistribution pattern (Yu: [0099], FIG. 9J: the planarization process removes portions of 108.).”
Regarding Claim 3,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 2, wherein the exposed surface of the first redistribution pattern is coplanar with an upper surface of the second insulating layer (Yu: [0099], FIG. 9J).”
Regarding Claim 4,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 3, further comprising, before forming the integrally formed first redistribution pattern, forming a first seed layer on a sidewall and a bottom surface of the first opening (Yu: seed layer 120, [0092], FIG. 9B, annotated FIG. 9E #1).”
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Yu: annotated FIG. 9E #1
Regarding Claim 5,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 4, further comprising, after forming the first seed layer: forming a resist pattern on the first insulating layer (Yu: photoresist layer 208, [0096], FIGs. 9C-9E), the resist pattern having a first guide opening (Yu: second trench openings 216, [0092], FIG. 9E), wherein the first redistribution pattern is formed in the first guide opening during forming the first redistribution pattern (Yu: FIG. 9F).”
Regarding Claim 6,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 5, further comprising, after forming the first redistribution pattern: removing the resist pattern to expose a portion of the first seed layer (Yu: FIGs. 9F-9G: In order to remove 120, 208 which is covering 120 must be removed first.), and removing the exposed portion of first seed layer by removing the resist pattern (Yu: [0096], FIGs. 9F-9G: 120 and 208 are removed in the same manufacturing step.).”
Regarding Claim 7,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 1, wherein the first redistribution pattern overlaps the semiconductor chip in a plan view (Lin: [0047], [0063], FIG. 3f, FIGS. 3g-3k: 220 overlaps openings 166. Openings 166 exposes 132 which is a pad overlying semiconductor die 124. Therefore, 220 overlaps 124.).”
Regarding Claim 8,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 1, wherein the semiconductor chip includes a chip pad (Lin: conductive layer 132, [0042], [0047], FIG. 3f), the chip pad provided on the surface of the semiconductor chip (Lin: [0042], FIG. 3f) and, wherein the first opening of the first insulating layer exposes the chip pad (Yu: FIG. 9A).”
Regarding Claim 9,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 1, wherein the first redistribution pattern includes a first via portion in the first opening (Yu: vias 225′, [0096]. FIG. 9G) and a first interconnection portion on the first via portion (Yu: second traces 226′, [0096], FIG. 9G), and wherein the first via portion is provided between the first interconnection portion and the semiconductor chip (Yu: FIG. 9G).”
Regarding Claim 11,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 1, further comprising after performing the planarization process: forming a third insulating layer (Yu: dielectric material 136, [0100], FIG. 9K) having a second opening on the first redistribution pattern (Yu: annotated FIG. 9K #1), the second opening exposing the first redistribution pattern (Yu: [0100], FIG. 9K: the RDL structure 960 is formed on the first RDL structure and is made according to the same or substantially similar process steps as described in FIGs. 9A-9J. Therefore, the formation of the second opening would be similar to that of the first opening. The formation of the first opening exposes the contact 104 because the opening 105 is made through the entirety of 106. Similarly, one of ordinary skill in the art would expect that the formation of the second opening would be made through the entirety of 136. Therefore the second opening would expose the first redistribution pattern.);forming a second redistribution pattern in the second opening and on the third insulating layer (Yu: conductive features 252, [0100], FIG. 9K);forming a fourth insulating layer covering the second redistribution pattern on the third insulating layer (Yu: second dielectric material 138, [0100], FIG. 9K); and performing a second planarization process on the fourth insulating layer (Yu: [0100]: The RDL structure 960 is formed on the first RDL structure and is made according to the same or substantially similar process steps as described in FIGs. 9A-9J. Therefore, the second RDL structure would experience a same manufacturing step as the first RDL structure in FIG. 9I.).”
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Annotated FIG. 9K #1
Regarding Claim 12,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 11, wherein the performing of the second planarization process on the fourth insulating layer comprises: removing the fourth insulating layer disposed on a surface of the second redistribution pattern; and planarizing the surface of the second redistribution pattern (Yu: [0099-0100], FIG. 9J: the planarization process removes portions of 108. The RDL structure 960 is formed on the first RDL structure and is made according to the same or substantially similar process steps as described in FIGs. 9A-9J. Therefore, a similar process to the process enacted on 108 in FIG. 9J would be enacted on 138. Therefore, a portion of the insulating layer disposed on a second redistribution pattern would be removed in a second planarization process.).”
Regarding Claim 13,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 12, further comprising, after performing the second planarization, forming a solder ball electrically connected to the second redistribution pattern above the surface of the second redistribution pattern (Yu: conductive connectors 168, [0103-0104]. FIG. 9L).”
Regarding Claim 14,
Lin/Yu teaches:
“A method of manufacturing a semiconductor package, comprising: providing a carrier substrate (Lin: carrier 190, [0078], FIG. 3c); disposing a semiconductor chip (Lin: semiconductor die 124, [0049], FIG. 3b) including a chip pad on the carrier substrate (Lin: conductive layer 132, [0042], [0047], FIG. 3f), the chip pad provided on a bottom surface of the semiconductor chip (Lin: FIG. 3c); forming a molding layer covering the semiconductor chip on the carrier substrate (Lin: encapsulant 198, [0058], FIG. 3c); removing the carrier substrate to expose the bottom surface of the semiconductor chip (Lin: surface 200, [101], FIG. 3d); turning the semiconductor chip to allow the bottom surface of the semiconductor chip to face upwards (Lin: FIGs. 3c-3d);forming a first insulating layer on the bottom surface of the semiconductor chip (Yu: first dielectric material 106, [0020], [0105] FIG. 8, FIG. 9C: The device made in FIGs. 9A-9L may be placed in FIG. 8. Therefore, the device of FIG. 9C must be flipped in order for the orientations of the device of FIG. 8 and 9C to be consistent.), the first insulating layer having a first opening to expose the chip pad (Yu: via openings 105, [0092], FIG. 9A); forming a first seed layer on a sidewall and a bottom surface of the first opening (Yu: seed layer 120, [0092], FIG. 9B, annotated FIG. 9E #1); forming a resist pattern on the first seed layer (Yu: photoresist layer 208, [0096], FIGs. 9C-9E), the resist pattern having a first guide opening (Yu: second trench openings 216, [0092], FIG. 9E); forming an integrally formed first redistribution pattern in the first opening and the first guide opening (Yu: conductive material 221, [0095], FIG. 9F); removing the resist pattern (Yu: [0096], FIG. 9G); forming a second insulating layer on the first insulating layer to cover the first redistribution pattern (Yu: second dielectric material 108 , [0099] FIG. 9I); removing the second insulating layer disposed on the first redistribution pattern to expose a surface of the first redistribution pattern (Yu: [0099], FIG. 9J); planarizing the exposed surface of the first redistribution pattern (Yu: [0099], FIG. 9J: the planarization process removes portions of 108 and planarizes 221 at once.); and forming a solder ball electrically connected to the first redistribution pattern above the surface of a second redistribution pattern (Yu: conductive connectors 168, [0103-0104]. FIG. 9L).”
Regarding Claim 15,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 14, further comprising, after removing the resist pattern, removing an exposed portion of first seed layer by removing the resist pattern (Yu: FIGs. 9F-9G: In order to remove 120, 208 which is covering 120 must be removed first.).”
Regarding Claim 16,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 14, wherein the first redistribution pattern overlaps the semiconductor chip in a plan view (Lin: [0047], [0063], FIG. 3f, FIGs. 3g-3k: 220 overlaps openings 166. Openings 166 expose 132 which is a pad overlying semiconductor die 124. Therefore, 220 overlaps 124.).”
Regarding Claim 17,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 14, wherein the first redistribution includes a first via portion in the first opening (Yu: vias 225′, [0096]. FIG. 9G) and a first interconnection portion on the first via portion (Yu: second traces 226′, [0096], FIG. 9G), and wherein the first via portion is provided between the first interconnection portion and the semiconductor chip (Yu: FIG. 9G).”
Regarding Claim 19,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 14, further comprising, before forming the solder ball:forming a third insulating layer (Yu: dielectric material 136, [0100], FIG. 9K) having a second opening on the first redistribution pattern (Yu: annotated FIG. 9K #1), the second opening exposing the first redistribution pattern (Yu: [0100], FIG. 9K: the RDL structure 960 is formed on the first RDL structure and is made according to the same or substantially similar process steps as described in FIGs. 9A-9J. Therefore, the formation of the second opening would be similar to that of the first opening. The formation of the first opening exposes the contact 104 because the opening 105 is made through the entirety of 106. Similarly, one of ordinary skill in the art would expect that the formation of the second opening would be made through the entirety of 136. Therefore the second opening would expose the first redistribution pattern.); forming the second redistribution pattern in the second opening and on the third insulating layer (Yu: conductive features 252, [0100], FIG. 9K); forming a fourth insulating layer covering the second redistribution pattern on the third insulating layer (Yu: second dielectric material 138, [0100], FIG. 9K); removing the fourth insulating layer disposed on a surface of the second redistribution pattern (Yu: [0100]: The RDL structure 960 is formed on the first RDL structure and is made according to the same or substantially similar process steps as described in FIGs. 9A-9J. Therefore, the second RDL structure would experience a same manufacturing step as the first RDL structure in FIG. 9I.); and planarizing the surface of the second redistribution pattern (Yu: [0100]: The RDL structure 960 is formed on the first RDL structure and is made according to the same or substantially similar process steps as described in FIGs. 9A-9J. Therefore, the second RDL structure would experience a same manufacturing step as the first RDL structure in FIG. 9I. The removal of the fourth insulating layer disposed on a surface of the second redistribution pattern is done through a planarization process.).”
Regarding Claim 20,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 19, wherein the second redistribution pattern includes a second via portion in the second opening (Yu: vias 255′, [0100], FIG. 9K) and a second interconnection portion on the second via portion (Yu: second traces 256′, [0100], FIG. 9K), and wherein the second via portion is provided between the second interconnection portion and the first redistribution pattern (Yu: FIG. 9K).”
Claims 10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lin/Yu as applied to claims 1-9, 11-17, and 19-20 above, and further in view of Yu et al #2 US 20140264930 A1. Yu et al #2 et al will be referenced to as Yu #2 henceforth.
Regarding Claim 10,
Lin/Yu teaches:
“The method of manufacturing the semiconductor package of claim 9,”
Lin/Yu doesn’t substantially teach:
“wherein a width of one surface of the first interconnection portion is a width in a range from 100% to 120% of a width of another surface of the first interconnection portion.”
However, Yu #2 teaches:
“wherein a width of one surface of the first interconnection portion is a width in a range from 100% to 120% of a width of another surface of the first interconnection portion (Yu #2: [0023], FIG. 2f: A lateral width w1 of the interconnection portion may be 10 μm to 110 μm. A width w3 of the interconnection portion may be 12 μm to 120 μm. If w1 is 10 μm and w3 is 12 μm, then the interconnection portion has a width of one surface which is 120% the width of another surface of the interconnection portion. These values of w1 and w3 are such that w3 is slightly wider than w1.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lin/Yu is modifiable in view of Yu #2 by implementing the dimensions of the interconnection in Yu #2 into Lin/Yu.
This is because this proportion of widths results in a flow of current from a contact pad being redistributed to a wider surface area. This lower concentration of current results in a smaller resistance and therefore less heat is generated. Excess heat in a semiconductor device may cause damage to device parts and therefore reduce the effectiveness of a semiconductor device.
Regarding Claim 18,
Lin/Yu/Yu # 2 teaches:
“The method of manufacturing the semiconductor package of claim 17, wherein a width of one surface of the first interconnection portion is a width in a range from 100% to 120% of a width of another surface of the first interconnection portion (Yu #2: [0023], FIG. 2f: A lateral width w1 of the interconnection portion may be 10 μm to 110 μm. A width w3 of the interconnection portion may be 12 μm to 120 μm. If w1 is 10 μm and w3 is 12 μm, then the interconnection portion has a width of one surface which is 120% the width of another surface of the interconnection portion. These values of w1 and w3 are such that w3 is slightly wider than w1.).”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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