DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/11/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: VERTICAL CHANNEL SEMICONDUCTOR MEMORY DEVICES.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation "contact plug" in line 27. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, "contact plug" in line 27 will be interpreted to read as "a contact plug".
In Re claims 17-20, they are rejected due to their dependence from claim 16. All rejections would be overcome by amending claim 16 as listed above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-9; 10-15; and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Juengling (US 2021/0134815 A1).
Re claim 1, Juengling discloses in FIGS. 30-35 a semiconductor device (10), comprising:
a substrate (11; [0043]);
bit line structures (20/30; [0046]) on the substrate (11), wherein the bit line structures (20/30) are spaced apart (separated) from each other in a first direction (left-to-right in FIG. 34) that is parallel (in line) with an upper surface (top plane) of the substrate (11), and each of the bit line structures (20/30) extends in a second direction (left-to-right in FIG. 35) that is parallel (in line) with the upper surface (top plane) of the substrate (11) and intersects (crosses) the first direction (left-to-right in FIG. 34);
channels (43; [0050]) on the bit line structures (20/30), wherein the channels (43) are electrically connected (by 44; [0065]) to the bit line structures (20/30) and spaced apart (separated) from each other in the first direction (left-to-right in FIG. 34);
a gate insulation pattern structure (left/right 58/62; [0053]) on sidewalls (left/right vertical planes) of each of the channels (43);
a gate electrode structure (left/right 56; [0053]) including:
a first gate electrode (left 56) on a first sidewall (left vertical plane) in the second direction (left-to-right in FIG. 35) of the gate insulation pattern structure (left/right 58/62); and
a second gate electrode (right 56) on a second sidewall (right vertical plane) in the second direction (left-to-right in FIG. 35) of the gate insulation pattern structure (left/right 58/64),
wherein the second sidewall (right vertical plane) of the gate insulation pattern structure (left/right 58/62) faces (across 43) the first sidewall (left vertical plane) of the gate insulation pattern structure (left/right 58/62) in the second direction (left-to-right in FIG. 35),
wherein the second gate electrode (right 56) is on a third sidewall (right vertical plane of right 58) in the first direction (left-to-right in FIG. 34) of an end portion (upper/lower and/or left/right edges) in the first direction (left-to-right in FIG. 34) of the gate insulation pattern structure (left/right 58/62), and
wherein the second gate electrode (right 56) is in contact (electrically by 68/70/72 in FIGS. 30-31; [0059]; and indirectly physically through left 58/43/right 58) with the first gate electrode (left 56); and
capacitors (75; [0059] and [0065]) on the channels (43), wherein the capacitors (75) are electrically connected (by 68/42; [0059] and [0065]) to the channels (43), respectively.
For the record, the examiner is interpreting “in contact with” and “electrically connected” to refer to objects being both in direct and indirect physical contact, and being both directly and indirectly electrically connected.
Re claim 2, Juengling discloses the semiconductor device according to claim 1, wherein the gate insulation pattern structure (left/right 58/62) includes: a first gate insulation pattern (left 58/62) that is in contact with a first sidewall (left vertical plane) in the second direction (left-to-right in FIG. 35) of each of the channels (43); and a second gate insulation pattern (right 58/62) that is in contact with a second sidewall (right vertical plane) in the second direction (left-to-right in FIG. 35) of each of the channels (43) and in contact with third (left) and fourth (right) sidewalls (vertical planes) in the first direction (left-to-right in FIG. 34) of each of the channels (43), wherein the second sidewall (right vertical plane) of each of the channels (43) faces (is across from) the first sidewall (left vertical plane) of each of the channels (43) in the second direction (left-to-right in FIG. 35), respectively, and wherein the fourth sidewall (right vertical plane) of each of the channels (43) faces (is across from) the third sidewall (left vertical plane) of each of the channels (43) in the second direction (left-to-right in FIG. 35), respectively.
Re claim 3, Juengling discloses the semiconductor device according to claim 2, wherein the first gate insulation pattern (left 58/62) includes a first material (silicon dioxide 62; [0053] and [0056]) and has a first thickness (width) in a plan view (FIG. 30), wherein the second gate insulation pattern (right 58/62) includes a second material (not silicon dioxide 58; [0056]) and has a second thickness (width) in the plan view (FIG. 30), and wherein the first material (silicon dioxide) is different from (not the same as) the second material (not silicon dioxide), and/or the first thickness (width) is different from (not the same as) the second thickness (width).
Re claim 6, Juengling discloses the semiconductor device according to claim 1, wherein an upper surface (top plane) of the gate electrode structure (left/right 56) is closer than an upper surface (top plane) of the gate insulation pattern structure (left/right 58/62) to the upper surface (top plane) of the substrate (11), and wherein a lower surface (bottom plane) of the gate electrode structure (left/right 56) is farther than a lower surface (bottom plane) of the gate insulation pattern structure (left/right 58/62) from the upper surface (top plane) of the substrate (11).
Re claims 7-8, Juengling discloses the semiconductor device according to claim 1, further comprising: a gate isolation pattern (64; [0055]) on the bit line structures (20/30), wherein the gate isolation pattern (64) is in contact with (through 62) an end portion (upper plane and sidewalls) in the first direction (left-to-right in FIG. 34) of the first gate electrode (left 56); and wherein the second gate electrode (right 56) overlaps (lies below) in the second direction (left-to-right in FIG. 35) with the gate isolation pattern (64).
Re claim 9, Juengling discloses the semiconductor device according to claim 1, further comprising: a contact plug (38/70; [0063]) that is in contact (physically and electrically; [0063]) with the second gate electrode (right 56).
Re claim 10, Juengling discloses in FIGS. 30-35 a semiconductor device (10), comprising:
a substrate (11; [0043]);
bit line structures (20/30; [0046]) on the substrate (11), wherein the bit line structures (20/30) are spaced apart (separated) from each other in a first direction (left-to-right in FIG. 34) that is parallel (in line) with an upper surface (top plane) of the substrate (11), and each of the bit line structures (20/30) extends in a second direction (left-to-right in FIG. 35) that is parallel (in line) with the upper surface (top plane) of the substrate (11) and intersects (crosses) the first direction (left-to-right in FIG. 34);
an insulation pattern structure (62; [0053]) on the bit line structures (20/30), wherein the insulation pattern structure (62) extends in the first direction (left-to-right in FIG. 34);
a gate isolation pattern (64; [0055]) that is in contact (physically touching) with an end portion (upper plane) in the first direction (left-to-right in FIG. 34) of the insulation pattern structure (62);
channels (43; [0050]) on the bit line structures (20/30), wherein the channels (43) are electrically connected (by 44; [0065]) to the bit line structures (20/30) and spaced apart (separated) from each other in the first direction (left-to-right in FIG. 34) on opposite sidewalls (left/right vertical planes) in the second direction (left-to-right in FIG. 35) of the insulation pattern structure (62);
a gate insulation pattern structure (left/right 58; [0053]) on the bit line structures (20/30), wherein the gate insulation pattern structure (left/right 58) is on the opposite sidewalls (left/right vertical planes) in the second direction (left-to-right in FIG. 35) of the insulation pattern structure (62) and sidewalls (left/right vertical planes) of the channels (43);
a gate electrode structure (left/right 56; [0053]) on the bit line structures (20/30), wherein the gate electrode structure (left/right 56) is on the opposite sidewalls (left/right vertical planes) in the second direction (left-to-right in FIG. 35) of the insulation pattern structure (62),
wherein the gate electrode structure (left/right 56) at least partially extends around (covers sidewalls of) the gate insulation pattern structure (left/right 58), and
wherein the gate electrode structure (left/right 56) overlaps (corresponds with) in the second direction (left-to-right in FIG. 35) with the gate isolation pattern (left/right 58); and
capacitors (75; [0059] and [0065]) on the channels (43), wherein the capacitors (75) are electrically connected (by 68/42; [0059] and [0065]) to the channels (43), respectively.
For the record, the examiner is interpreting “in contact with” and “electrically connected” to refer to objects being both in direct and indirect physical contact, and being both directly and indirectly electrically connected.
Re claim 11, Juengling discloses the semiconductor device according to claim 10, wherein the gate electrode structure (left/right 56) is on opposite sidewalls (left/right vertical planes) in the second direction (left-to-right in FIG. 35) of the gate insulation pattern structure (left/right 58) and a sidewall (left vertical plane) in the first direction (left-to-right in FIG. 34) of an end portion (top plane) in the first direction (left-to-right in FIG. 34) of the gate insulation pattern structure (left/right 58).
Re claim 12, Juengling discloses the semiconductor device according to claim 10, wherein the gate electrode structure (left/right 56; [0053]) includes a first gate electrode (left 56) on a first sidewall (left vertical plane) in the second direction (left-to-right in FIG. 35) of the gate insulation pattern structure (left/right 58/62); and
a second gate electrode (right 56) on a second sidewall (right vertical plane) in the second direction (left-to-right in FIG. 35) of the gate insulation pattern structure (left/right 58/64),
wherein the second sidewall (right vertical plane) of the gate insulation pattern structure (left/right 58) faces (across 43) the first sidewall (left vertical plane) of the gate insulation pattern structure (left/right 58) in the second direction (left-to-right in FIG. 35), and
wherein the second gate electrode (right 56) is on a third sidewall (right vertical plane of right 58) in the first direction (left-to-right in FIG. 34) of an end portion (upper/lower and/or left/right edges) in the first direction (left-to-right in FIG. 34) of the gate insulation pattern structure (left/right 58).
Re claim 13, Juengling discloses the semiconductor device according to claim 12, wherein the second gate electrode overlaps in the second direction with the gate isolation pattern (see claim 8).
Re claim 14, Juengling discloses the semiconductor device according to claim 10, wherein the gate insulation pattern structure (left/right 58) includes: a first gate insulation pattern on a first sidewall in the second direction among the sidewalls of each of the channels; and a second gate insulation pattern that is in contact with a second sidewall in the second direction among the sidewalls of each of the channels and in contact with third and fourth sidewalls in the first direction among the sidewalls of each of the channels, wherein the second sidewall of each of the channels faces the first sidewall of each of the channels in the second direction, respectively, and wherein the fourth sidewall of each of the channels faces the third sidewall of each of the channels in the first direction, respectively (see claim 2).
Re claim 15, Juengling discloses the semiconductor device according to claim 14, wherein the second gate insulation pattern (right 58) is in contact (through 62) with a sidewall (left vertical plane) of the first gate insulation pattern (left 58) between adjacent (side-by-side) channels (43) in the first direction (left-to-right in FIG. 34) among the channels (43).
Re claim 16, Juengling discloses in FIGS. 30-35 a semiconductor device, comprising:
a substrate (11; [0043]);
bit line structures (20/30; [0046]) on the substrate (11), wherein the bit line structures (20/30) are spaced apart (separated) from each other in a first direction (left-to-right in FIG. 34) that is parallel (in line) with an upper surface (top plane) of the substrate (11), and each of the bit line structures (20/30) extends in a second direction (left-to-right in FIG. 35) that is parallel (in line) with the upper surface (top plane) of the substrate (11) and intersects (crosses) the first direction (left-to-right in FIG. 34);
an insulation pattern structure (62; [0053]) on the bit line structures (20/30), wherein the insulation pattern structure (62) extends in the first direction (left-to-right in FIG. 34);
channels (43; [0050]) on the bit line structures (20/30), wherein the channels (43) are electrically connected (by 44; [0065]) to the bit line structures (20/30) and spaced apart (separated) from each other in the first direction (left-to-right in FIG. 34) on opposite sidewalls (left/right vertical planes) in the second direction (left-to-right in FIG. 35) of the insulation pattern structure (62);
a gate isolation pattern (64; [0055]) that is in contact (physically touching) with an end portion (upper plane) in the first direction (left-to-right in FIG. 34) of the insulation pattern structure (62);
a gate insulation pattern structure (left/right 58; [0053]) on sidewalls (left/right vertical planes) of each of the channels (43);
a gate electrode structure (left/right 56; [0053]) including:
a first gate electrode (left 56) on a first sidewall (left vertical plane) in the second direction (left-to-right in FIG. 35) of the gate insulation pattern structure (left/right 58/62); and
a second gate electrode (right 56) on a second sidewall (right vertical plane) in the second direction (left-to-right in FIG. 35) of the gate insulation pattern structure (left/right 58/64),
wherein the second sidewall (right vertical plane) of the gate insulation pattern structure (left/right 58/62) faces (across 43) the first sidewall (left vertical plane) of the gate insulation pattern structure (left/right 58/62) in the second direction (left-to-right in FIG. 35),
wherein the second gate electrode (right 56) is on a third sidewall (right vertical plane of right 58) in the first direction (left-to-right in FIG. 34) of an end portion (upper/lower and/or left/right edges) in the first direction (left-to-right in FIG. 34) of the gate insulation pattern structure (left/right 58/62), and
wherein the second gate electrode (right 56) is in contact (electrically by 68/70/72 in FIGS. 30-31; [0059]; and indirectly physically through left 58/43/right 58) with the first gate electrode (left 56);
capacitors (75; [0059] and [0065]) on the channels (43), wherein the capacitors (75) are electrically connected (by 68/42; [0059] and [0065]) to the channels (43); and
a contact plug (38/70; [0063]) that is in contact (physically and electrically; [0063]) with the second gate electrode (right 56).
For the record, the examiner is interpreting “in contact with” and “electrically connected” to refer to objects being both in direct and indirect physical contact, and being both directly and indirectly electrically connected.
Re claim 17, Juengling discloses the semiconductor device according to claim 16, wherein the first gate electrode (left 56) contacts (directly and indirectly) the opposite sidewalls (left/right vertical planes) in the second direction (left-to-right in FIG. 35) of the insulation pattern structure (62).
Re claim 18, Juengling discloses the semiconductor device according to claim 16, wherein the second gate electrode overlaps in the second direction with the gate isolation pattern (see claim 8).
Re claim 19, Juengling discloses the semiconductor device according to claim 16, wherein the gate insulation pattern structure includes: a first gate insulation pattern on a first sidewall in the second direction among the sidewalls of each of the channels; and a second gate insulation pattern that is in contact with a second sidewall in the second direction among the sidewalls of each of the channels and third and fourth sidewalls in the first direction among the sidewalls of each of the channels, wherein the second sidewall of each of the channels faces the first sidewall of each of the channels in the second direction, respectively, and wherein the fourth sidewall of each of the channels faces the third sidewall of each of the channels in the first direction, respectively (see claim 2).
Re claim 20, Juengling discloses the semiconductor device according to claim 16, wherein the second gate electrode (right 56) includes: an extension portion (part of 56 protruding beyond each 43) that extends in the first direction (left-to-right in FIGS. 30 and 34); and a protruding portion (part of 56 overlapping 58) that protrudes (extends) from the extension portion (part of 56 protruding beyond each 43) in the second direction (left-to-right in FIGS. 30 and 35).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Juengling in view CHANG et al (US 2023/0284431 A1, hereafter Chang).
Re claim 4, Juengling discloses the semiconductor device according to claim 3, wherein the first material (62) includes an oxide ([0053] and [0056]), a nitride, and/or air.
But, fails to disclose wherein each of the first material (62) and the second material (58) includes an oxide, a nitride, and/or air.
However,
Chang discloses in FIG. 1B a semiconductor device, comprising: wherein each of a first material (110/112) and the second material (104) includes an oxide (SiOx; [0030] and [0048]), a nitride (SixNy; [0030] and [0048]), and/or air.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Juengling, by using the first and second materials of Chang, such that each of the first material (62) and the second material (58) includes an oxide, a nitride, and/or air, producing an integral structure with the same properties (e.g. dielectric constant, RC-time constant and etch selectivity) for uniform characteristics of the individual devices.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Juengling in view GOKI et al (US 2018/0076266 A1, hereafter Goki).
Re claim 5, Juengling discloses the semiconductor device according to claim 1, wherein the first gate electrode (left 56) includes a first material (unspecified conductive material; [0051]) and has a first thickness (extension) in a plan view (FIG. 30), wherein the second gate electrode (right 56) includes a second material (unspecified conductive material; [0051]) and has a second thickness (extension) in a plan view (FIG. 30).
But, fails to disclose and wherein the first material is different from the second material, and/or the first thickness is different from the second thickness.
However,
Goki discloses in FIG. 5 a semiconductor device, comprising: wherein a first gate electrode (left 20; [0016]) includes a first material (Si; [0016]) and has a first thickness (L1; [0026]) in a plan view (FIG. 5), wherein a second gate electrode (right 2; [0016]) includes a second material (Si; [0016]) and has a second thickness (upward extension) in a plan view (FIG. 5), and the first thickness (L1) is different from (not the same as) the second thickness (upward extension).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Juengling, by using the first and second thicknesses of Goki, such that the first thickness is different from the second thickness, thereby, the area of the device channel formed on the side of the first gate electrode is larger than the area of a vertical channel. Therefore, the electrical resistance of the channel is lower and the ON-resistance of the semiconductor device is lower (Goki; [0026]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 11373914 B2 and US 11398571 B2 disclose vertical transistors similar to Juengling used for each of claims 1; 10; and 16. However, these prior art reference disclose tapered transistor channels without bit lines formed on a separate and distinct substrate as required for each of claims 1; 10; and 16 in the pursuit of increased aspect ratio vertical channel transistors without the vertical channels bending or collapsing.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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