DETAILED ACTION
This action is responsive to the following communications: the Application filed on June 11, 2024 and Provisional application No. 63/472,712 filed on June 13, 2023.
Claims 1-20 are pending. Claims 1, 19 and 20 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-9 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190066818) in view of Aritome (US 20070253256).
Regarding independent claim 1, Lee et al. disclose a system [Fig. 2: 100] comprising:
a set of memory components of a memory sub-system [see Fig. 2, controller 112 includes a front-end module 208 that interfaces with a host, a back-end module 210 that interfaces with the one or more non-volatile memory die 108, para. 48]; and
at least one processing device [Fig. 2: 112, para. 52-53] operatively coupled to the set of memory components, the at least one processing device being configured to perform operations comprising:
receiving a request to program data to an individual memory component of the set of memory components [see Fig. 7A, before step 702, controller 122 would receive host data and an instruction to program from the host. In step 702, controller 122 sends instructions to one or more memory die 108 to program data, para. 87-88];
selectively adjusting a program voltage (Vpgm) associated with a subset of word lines (WLs) of the individual memory component based on whether the subset of WLs is associated with an individual WL group (WLG) [word lines are split into groups and the device defines different programming parameters for world line group, including an additional program voltage offset on top of the default programming voltage. These parameters can specify higher starting voltages, bigger step sizes and/or other variations in the programming waveform, para. 71 as well as 103-104]; and
programming the data to the individual memory component according to the selectively adjusted Vpgm [see Fig. 7B: step 772, para. 90].
However, Lee et al. are silent with respect to determining that a program erase count (PEC) associated with the individual memory component transgresses a threshold value;
in response to determining that the PEC associated with the individual memory component transgresses the threshold value, selectively adjusting a program voltage (Vpgm) associated with a subset of word lines (WLs) of the individual memory component based on whether the subset of WLs is associated with an individual WL group (WLG).
Aritome teaches determining that a program erase count (PEC) associated with the individual memory component transgresses a threshold value [the quantity of program/erase cycles performed on a memory block can be referred to as an "experience count," or "hot count". The hot count of a memory array, and/or of each memory block within the memory array, can be monitored by a system controller, para. 36];
in response to determining that the PEC associated with the individual memory component transgresses the threshold value, selectively adjusting a program voltage (Vpgm) associated with a word line in a memory block [see Figs. 2A-2B and 3, programming voltage changes at threshold values of 100, 1,000, or 10,000 cycles, embodiments are not so limited. That is, embodiments of the present disclosure are not limited to adjusting a programming voltage after predetermined threshold hot count values (e.g., processing cycles), para. 60].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply Aritome’s PEC-based adjustment to per WL group programming parameters as taught by Lee et al. such that adjust the Vpgm used for a subset of word lines depending on which WL group they are in once PEC exceeds a threshold value to improve programming reliability predictably and improve data retention.
Regarding claim 2, Lee et al. in combination with Aritome teach the limitations with respect to claim 1.
Furthermore, Lee et al. disclose the memory sub-system comprises a three-dimensional (3D) NAND memory [FIGS. 4B-4G depict an example 3D NAND structure, para. 59].
Regarding claim 3, Lee et al. in combination with Aritome teach the limitations with respect to claim 1.
Furthermore, Lee et al. disclose the operations comprising:
determining that a first set of WLs of the individual memory component is associated with a first WLG [see Fig. 4D, the word lines can be split into word line groups (higher word line group and lower word line group) and treated differently, para. 70 as well as 103];
determining that a second set of WLs of the individual memory component is associated with a second WLG [see Fig. 4D, the word lines can be split into word line groups (higher word line group and lower word line group) and treated differently, para. 70 as well as 103];
adjusting the Vpgm associated with the first set of WLs in response to determining that the first set of WLs are associated with the first WLG [slower to program word line groups can start the programming voltage staircase waveform at a higher value, starting the programming voltage (Vpgm) at a raised voltage level that is offset above a default value by some amount, para. 103]; and
programming data to the individual memory component using the adjusted Vpgm for the first set of WLs and using the Vpgm for the second set of WLs [WLG programming parameters mean one WLG can use an offset Vpgm while other uses the default Vpgm, para. 71].
Regarding claim 6, Lee et al. in combination with Aritome teach the limitations with respect to claim 1.
Furthermore, Lee et al. disclose the operations comprising:
accessing configuration data comprising a table that associates different WLGs with respective Vpgm adjustments based on PEC values [Lee et al. disclose a look up table can be used to store parameters, para. 141. A person of ordinary skill in the art would have found it obvious to implement a table to store the combined Lee et al.’s WLGs Vpgm adjustments and Aritome’s PEC value].
Regarding claim 7, Lee et al. in combination with Aritome teach the limitations with respect to claim 6.
Furthermore, Lee et al. disclose wherein the table [Lee et al. disclose a look up table can be used to store parameters, para. 141] comprises:
a first WLG associated with a first Vpgm [parameters select which WLGs get additional program voltage offsets on top of default and WLGs can start Vpgm at a offset level, para. 71 as well as para. 103-104].
Aritome discloses a first PEC threshold associated with a first adjustment to the first Vpgm [Figs. 2A-2B and 3 depict programming voltage changes at threshold values of 100, 1,000, or 10,000 cycles, embodiments are not so limited. That is, embodiments of the present disclosure are not limited to adjusting a programming voltage after predetermined threshold hot count values (e.g., processing cycles), para. 60]; and
a second PEC threshold associated with a second adjustment to the first Vpgm [Figs. 2A-2B and 3 depict programming voltage changes at threshold values of 100, 1,000, or 10,000 cycles, embodiments are not so limited. That is, embodiments of the present disclosure are not limited to adjusting a programming voltage after predetermined threshold hot count values (e.g., processing cycles), para. 60. A person of ordinary skill in the art would have found it obvious to implement a table to store the combined Lee et al.’s WLGs Vpgm adjustments and Aritome’s PEC value].
Regarding claim 8, Lee et al. in combination with Aritome teach the limitations with respect to claim 7.
Furthermore, Lee et al. disclose wherein the table [Lee et al. disclose a look up table can be used to store parameters, para. 141] further comprises:
a second WLG associated with a second Vpgm [parameters select which WLGs get additional program voltage offsets on top of default and WLGs can start Vpgm at a offset level, para. 71 as well as para. 103-104].
Aritome discloses a first PEC threshold associated with a third adjustment to the second Vpgm [Figs. 2A-2B and 3 depict programming voltage changes at threshold values of 100, 1,000, or 10,000 cycles, embodiments are not so limited. That is, embodiments of the present disclosure are not limited to adjusting a programming voltage after predetermined threshold hot count values (e.g., processing cycles), para. 60]; and
a second PEC threshold associated with a fourth adjustment to the second Vpgm [Figs. 2A-2B and 3 depict programming voltage changes at threshold values of 100, 1,000, or 10,000 cycles, embodiments are not so limited. That is, embodiments of the present disclosure are not limited to adjusting a programming voltage after predetermined threshold hot count values (e.g., processing cycles), para. 60. A person of ordinary skill in the art would have found it obvious to implement a table to store the combined Lee et al.’s WLGs Vpgm adjustments and Aritome’s PEC value].
Regarding claim 9, Lee et al. in combination with Aritome teach the limitations with respect to claim 1.
Furthermore, Lee et al. disclose adjusting the Vpgm comprises applying a step static threshold voltage to the Vpgm [para. 100].
Regarding claim 17, Lee et al. in combination with Aritome teach the limitations with respect to claim 1.
Furthermore, Aritome disclose wherein the threshold value comprises at least 3000 PEC [programming voltage changes at threshold values of 100, 1,000, or 10,000 cycles, embodiments are not so limited, para. 60. Therefore, A person of ordinary skill in the art would have found it obvious to choose the threshold value has at least 3000 PEC].
Regarding claim 18, Lee et al. in combination with Aritome teach the limitations with respect to claim 1.
Furthermore, Aritome et al. disclose wherein the threshold value comprises a first threshold value, the operations comprising:
adjusting the Vpgm associated with the subset of WLs by a second amount in response to determining that the PEC associated with the individual memory component transgresses a second threshold value that is greater than the first threshold value [see FIGS. 2A-2B and 3, adjusting a programming voltage after predetermined threshold hot count values (e.g., processing cycles), so programming voltage changes at threshold values of 100, 1,000, or 10,000 cycles, para. 60].
Regarding independent claim 19, Lee et al. disclose a method comprising:
receiving a request to program data to an individual memory component of the set of memory components [see Fig. 7A, before step 702, controller 122 would receive host data and an instruction to program from the host. In step 702, controller 122 sends instructions to one or more memory die 108 to program data, para. 87-88];
selectively adjusting a program voltage (Vpgm) associated with a subset of word lines (WLs) of the individual memory component based on whether the subset of WLs is associated with an individual WL group (WLG) [word lines are split into groups and the device defines different programming parameters for world line group, including an additional program voltage offset on top of the default programming voltage. These parameters can specify higher starting voltages, bigger step sizes and/or other variations in the programming waveform, para. 71 as well as 103-104]; and
programming the data to the individual memory component according to the selectively adjusted Vpgm [see Fig. 7B: step 772, para. 90].
However, Lee et al. are silent with respect to determining that a program erase count (PEC) associated with the individual memory component transgresses a threshold value;
in response to determining that the PEC associated with the individual memory component transgresses the threshold value, selectively adjusting a program voltage (Vpgm) associated with a subset of word lines (WLs) of the individual memory component based on whether the subset of WLs is associated with an individual WL group (WLG).
Aritome teaches determining that a program erase count (PEC) associated with the individual memory component transgresses a threshold value [the quantity of program/erase cycles performed on a memory block can be referred to as an "experience count," or "hot count". The hot count of a memory array, and/or of each memory block within the memory array, can be monitored by a system controller, para. 36];
in response to determining that the PEC associated with the individual memory component transgresses the threshold value, selectively adjusting a program voltage (Vpgm) associated with a word line in a memory block [see Figs. 2A-2B and 3, programming voltage changes at threshold values of 100, 1,000, or 10,000 cycles, embodiments are not so limited. That is, embodiments of the present disclosure are not limited to adjusting a programming voltage after predetermined threshold hot count values (e.g., processing cycles), para. 60].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply Aritome’s PEC-based adjustment to per WL group programming parameters as taught by Lee et al. such that adjust the Vpgm used for a subset of word lines depending on which WL group they are in once PEC exceeds a threshold value to improve programming reliability predictably and improve data retention.
Regarding independent claim 20, Lee et al. disclose a non-transitory computer-readable storage medium comprising instructions that, when executed by at least one processing device [Fig. 2: 112, para. 52-53], cause the at least one processing device to perform operations comprising:
receiving a request to program data to an individual memory component of the set of memory components [see Fig. 7A, before step 702, controller 122 would receive host data and an instruction to program from the host. In step 702, controller 122 sends instructions to one or more memory die 108 to program data, para. 87-88];
selectively adjusting a program voltage (Vpgm) associated with a subset of word lines (WLs) of the individual memory component based on whether the subset of WLs is associated with an individual WL group (WLG) [word lines are split into groups and the device defines different programming parameters for world line group, including an additional program voltage offset on top of the default programming voltage. These parameters can specify higher starting voltages, bigger step sizes and/or other variations in the programming waveform, para. 71 as well as 103-104]; and
programming the data to the individual memory component according to the selectively adjusted Vpgm [see Fig. 7B: step 772, para. 90].
However, Lee et al. are silent with respect to determining that a program erase count (PEC) associated with the individual memory component transgresses a threshold value;
in response to determining that the PEC associated with the individual memory component transgresses the threshold value, selectively adjusting a program voltage (Vpgm) associated with a subset of word lines (WLs) of the individual memory component based on whether the subset of WLs is associated with an individual WL group (WLG).
Aritome teaches determining that a program erase count (PEC) associated with the individual memory component transgresses a threshold value [the quantity of program/erase cycles performed on a memory block can be referred to as an "experience count," or "hot count". The hot count of a memory array, and/or of each memory block within the memory array, can be monitored by a system controller, para. 36];
in response to determining that the PEC associated with the individual memory component transgresses the threshold value, selectively adjusting a program voltage (Vpgm) associated with a word line in a memory block [see Figs. 2A-2B and 3, programming voltage changes at threshold values of 100, 1,000, or 10,000 cycles, embodiments are not so limited. That is, embodiments of the present disclosure are not limited to adjusting a programming voltage after predetermined threshold hot count values (e.g., processing cycles), para. 60].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply Aritome’s PEC-based adjustment to per WL group programming parameters as taught by Lee et al. such that adjust the Vpgm used for a subset of word lines depending on which WL group they are in once PEC exceeds a threshold value to improve programming reliability predictably and improve data retention.
Claims 10-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190066818) in view of Aritome (US 20070253256) as applied to claim 3 above, and further in view of Wakchaure et al. (US 20150092488).
Regarding claim 10, Lee et al. in combination with Aritome teach the limitations with respect to claim 1.
However, Lee et al. in combination with Aritome are silent with respect to the operations comprising:
determining a current temperature associated with the memory sub-system; and
selecting an adjustment value to apply to the Vpgm based on the current temperature.
Wakchaure et al. teach the operations comprising:
determining a current temperature associated with the memory sub-system [most SSDs have a reliable temperature sensor on the board (e.g., thermally proximate to or thermally coupled to the NVM/NAND flash memory 152 and/or controller logic 150) and SSD firmware can have access to instantaneous operating temperature of the drive, para. 21]; and
selecting an adjustment value to apply to the Vpgm based on the current temperature [a flash drive's operating temperature information is used to select appropriate trim values, para. 20. A "trim profile" generally refers to pre-defined setting(s) for NVM/NAND memory parameters that includes settings for parameters such as WL/BL (Word Line/Bit Line) voltages during array operations (e.g., program/erase/read/etc.), program verify levels, read reference values, maximum WL bias value, array operation timeout period, etc., para. 22].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teaching of Wakchaure et al. to the teaching of Lee et al. in combination with Aritome such that incorporating Wakchaure et al.’s temperature based trim selection into the controller of Lee et al. in combination with Aritome so that the controller selects an adjustment value to apply to the Vpgm based on the current temperature, improving flash memory endurance and improving program disturb performance at higher temperatures without changing the fundamental programming scheme [see Wakchaure et al.’s para. 13].
Regarding claim 11, Lee et al. in combination with Aritome and Wakchaure et al. teach the limitations with respect to claim 10.
Furthermore, Wakchaure et al. disclose the operations comprising:
determining that the current temperature is below a threshold temperature value [see Fig. 3: step 306, drive temperature is less than some fixed threshold temperature (Tc) at determined, para. 24]; and
in response to determining that the current temperature is below the threshold temperature value, applying a first adjustment to the Vpgm associated with the subset of WLs [see Fig. 3, once the sense drive temperature drops below the threshold temperature value (Tc) as determined at operation 310, trim profile A is reloaded at operation 302, para. 24].
Regarding claim 12, Lee et al. in combination with Aritome and Wakchaure et al. teach the limitations with respect to claim 11.
Furthermore, Wakchaure et al. disclose the operations comprising:
determining that the current temperature is above the threshold temperature value [see Fig. 3: step 310, the sensed drive temperature stays above the threshold temperature value (Tc), para. 24]; and
in response to determining that the current temperature is above the threshold temperature value, applying a second adjustment to the Vpgm associated with the subset of WLs [see Fig. 3, as long as the sensed drive temperature stays above the threshold temperature value (Tc), as determined at an operation 310, the drive continues with trim profile B at operation 312, para. 24].
Regarding claim 13, Lee et al. in combination with Aritome and Wakchaure et al. teach the limitations with respect to claim 12.
Furthermore, Wakchaure et al. disclose wherein the second adjustment is lower than the first adjustment [Wakchaure et al. disclose two different dependent settings (trim profile A and trim profile B). Wakchaure et al. also disclose a trim profile may include settings for parameters such as WL/BL (Word Line/Bit Line) voltages during array operations (e.g., program/erase/read/etc.), program verify levels, read reference values, maximum WL bias value, array operation timeout period, etc., para. 22. A person of ordinary skill in the art would have found it obvious to choose one trim profile is lower than the other].
Regarding claim 15, Lee et al. in combination with Aritome and Wakchaure et al. teach the limitations with respect to claim 10.
Furthermore, Wakchaure et al. disclose the operations comprising:
storing first and second tables, the first table comprising a first set of adjustments to apply to Vpgms of WLGs when the current temperature is below a threshold temperature value, the second table comprising a second set of adjustments to apply to Vpgms of WLGs when the current temperature is above the threshold temperature value [Wakchaure et al. disclose choosing two different dependent settings (trim profile A and trim profile B) based on drive temperature is below or above the threshold temperature value (Tc), see Fig. 3, para. 24. Wakchaure et al. also disclose a trim profile may include settings for parameters such as WL/BL (Word Line/Bit Line) voltages during array operations (e.g., program/erase/read/etc.), program verify levels, read reference values, maximum WL bias value, array operation timeout period, etc., para. 22].
Regarding claim 16, Lee et al. in combination with Aritome and Wakchaure et al. teach the limitations with respect to claim 15.
Furthermore, Wakchaure et al. disclose the operations comprising:
selectively accessing one of the first and second tables based on the current temperature of the memory sub-system [Wakchaure et al. disclose choosing two different dependent settings (trim profile A and trim profile B) based on drive temperature is below or above the threshold temperature value (Tc), see Fig. 3, para. 24].
Allowable Subject Matter
Claims 4-5 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 4, the applied prior arts Lee et al. and Aritome, individually or in combination, do not teach or suggest the first WLG comprises a first plurality of WLs having a first reliability value that falls below a reliability threshold, and wherein the second WLG comprises a second plurality of WLs having a second reliability value that exceeds the reliability threshold.
Thus, there is no teaching or suggestion in the prior art of record to provide the recited the first WLG comprises a first plurality of WLs having a first reliability value that falls below a reliability threshold, and wherein the second WLG comprises a second plurality of WLs having a second reliability value that exceeds the reliability threshold.
With respect to claim 14, the applied prior arts Lee et al., Aritome and Wakchaure et al., individually or in combination, do not teach or suggest identifying a second subset of WLs associated with a second WLG having a Vpgm that is associated with an adjustment to a corresponding Vpgm when the current temperature is below the threshold temperature value and for which the corresponding Vpgm remains unchanged when the current temperature is above the threshold temperature value.
Thus, there is no teaching or suggestion in the prior art of record to provide the recited the operations comprising identifying a second subset of WLs associated with a second WLG having a Vpgm that is associated with an adjustment to a corresponding Vpgm when the current temperature is below the threshold temperature value and for which the corresponding Vpgm remains unchanged when the current temperature is above the threshold temperature value.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825