DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-11 and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species (B) and Modification (C2), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 21 August 2026.
Applicant’s election without traverse of Species A, Modification C1 in the reply filed on 21 August 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11 June 2024 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8-9 and 12 are rejected under 35 U.S.C. 102 (a)(1)(2) as being anticipated by Tsuyoshi Oota et al. (US 9,887,285 B1; hereinafter “Oota”).
Regarding Claim 1, Oota teaches a semiconductor device comprising:
a substrate comprising a cell region (22, Fig. 19 and Fig. 20, column 3, lines 61-62 describe an n+ type region upon which a drift layer is disposed wherein Fig. 16 and Fig. 17 depict a cell region of the substrate 22);
a first well region in the cell region of the substrate (FW and 29, annotated Fig. 20, column 9, line 57 describes a p-type body region 29 comprising a first well region FW in the cell region of the substrate 22);
a second well region disposed in the cell region and spaced apart from the first well region in a first direction (SW and 29, annotated Fig. 20, column 9, line 57 describes the p-type body region 29 comprising a second well region SW in the cell region of the substrate 22 spaced apart from the first well region FW in a first direction FW);
a third well region disposed in the cell region and spaced apart from the first well region in a second direction intersecting the first direction (29 and TW, annotated Fig. 17, Fig. 19 and Fig. 20, column 9, line 57 describes the p-type body region 29 comprising a third well TW disposed in the cell region and spaced apart from the first well FW in a second direction SD intersecting the first direction FD as shown in annotated Fig. 17);
a first gate portion disposed in overlap with a part of the first well region and a part of the third well region (FG and 18, annotated Fig. 18 and annotated Fig. 20, column 3, lines 59-60 describe a gate electrode 18 wherein annotated Fig. 18 depicts a first gate portion FG as shown disposed above and overlapping the first well region FW and third well region TW in annotated Fig. 20); and
a second gate portion disposed in overlap with a part of the second well region (SG and 18, annotated Fig. 18 and annotated Fig. 20, column 3, lines 59-60 describe the gate electrode 18 wherein annotated Fig. 18 depicts a second gate portion SG as shown disposed above and overlapping the second well region SW in annotated Fig. 20),
wherein the first gate portion and the second gate portion are spaced apart from each other (FG and SG, annotated Fig. 18 and annotated Fig. 20 depict wherein the first gate portion FG and second gate portion SG are spaced apart from each other).
PNG
media_image1.png
486
599
media_image1.png
Greyscale
PNG
media_image2.png
473
606
media_image2.png
Greyscale
PNG
media_image3.png
434
552
media_image3.png
Greyscale
Regarding Claim 8, Oota teaches the semiconductor device of claim 1, comprising:
a first channel region being a portion of the first well region and disposed along an edge of the first well region (FW, 29, annotated Fig. 20, column 16, lines 30-33 describes wherein a surface of the well region 29 comprising the first well region FW functions as a channel region wherein the surface of the first well region FW comprises an edge resulting in a first channel region being at least a portion of the first well region FW and disposed along an edge of the first well region FW);
a second channel region being a portion of the second well region and disposed along an edge of the second well region (SW, 29, annotated Fig. 20, column 16, lines 30-33 describes wherein the surface of the well region 29 comprising the second well region SW functions as a channel region wherein the surface of the second well region SW comprises an edge resulting in a second channel region being at least a portion of the second well region SW and disposed along an edge of the second well region SW); and
a third channel region being a portion of the third well region and disposed along an edge of the third well region (TW, 29, annotated Fig. 20, column 16, lines 30-33 describes wherein the surface of the well region 29 comprising the third well region TW functions as a channel region wherein the surface of the third well region TW comprises an edge resulting in a third channel region being at least a portion of the third well region TW and disposed along an edge of the third well region TW),
wherein the first gate portion is disposed on the first channel region (FG and FW, annotated Fig. 20 depicts wherein the first gate portion FG is disposed on the first well region FW comprising the first channel region at the edge resulting in the first gate portion FG being disposed on the first channel region), and
the second gate portion is disposed on the second channel region and is non-overlapped with the first channel region (SG and SW, annotated Fig. 20 depicts wherein the second gate portion SG is disposed on the second well region SW comprising the second channel region at the edge resulting in the second gate portion SG being disposed on the second channel region wherein the second gate portion SG does not overlap the first well region FW and therefore not overlapping the first channel region).
Regarding Claim 9, Oota teaches the semiconductor device of claim 8, further comprising a third gate portion disposed on the first well region and the third well region (TG, FW and TW, annotated Fig. 19, column 3, lines 59-60 describe the gate electrode 18 wherein annotated Fig. 19 depicts a third gate portion TG as shown disposed above and overlapping the first well region FW) and disposed to overlap the first channel region (TG and FW, annotated Fig. 19, column 16, lines 30-33 describes wherein the surface of the well region 29 comprising the first well region FW comprises the first channel region along the surface wherein the third gate region TR is overlapping the edge of the first well region FW and therefore the first channel region) and the third channel region (TG and TW, annotated Fig. 19, column 16, lines 30-33 describes wherein the surface of the well region 29 comprising the third well region TW comprises the third channel region along the surface wherein the third gate region TR is overlapping the edge of the third well region TW and therefore the third channel region).
Regarding Claim 12, Oota teaches a semiconductor device comprising:
a substrate comprising a cell region (22, Fig. 19 and Fig. 20, column 3, lines 61-62 describe an n+ type region upon which a drift layer is disposed wherein Fig. 16 and Fig. 17 depict a cell region of the substrate 22);
a first well region in the cell region of the substrate (FW and 29, annotated Fig. 20, column 9, line 57 describes a p-type body region 29 comprising a first well region FW in the cell region of the substrate 22);
a second well region disposed in the cell region and spaced apart from the first well region in a first direction (SW and 29, annotated Fig. 20, column 9, line 57 describes the p-type body region 29 comprising a second well region SW in the cell region of the substrate 22 spaced apart from the first well region FW in a first direction FW);
a third well region disposed in the cell region and spaced apart from the first well region in a second direction intersecting the first direction (29 and TW, annotated Fig. 17, Fig. 19 and Fig. 20, column 9, line 57 describes the p-type body region 29 comprising a third well TW disposed in the cell region and spaced apart from the first well FW in a second direction SD intersecting the first direction FD as shown in annotated Fig. 17);
a first channel region being a portion of the first well region and disposed along an edge of the first well region (FW, 29, annotated Fig. 20, column 16, lines 30-33 describes wherein a surface of the well region 29 comprising the first well region FW functions as a channel region wherein the surface of the first well region FW comprises an edge resulting in a first channel region being at least a portion of the first well region FW and disposed along an edge of the first well region FW);
a second channel region being a portion of the second well region and disposed along an edge of the second well region (SW, 29, annotated Fig. 20, column 16, lines 30-33 describes wherein the surface of the well region 29 comprising the second well region SW functions as a channel region wherein the surface of the second well region SW comprises an edge resulting in a second channel region being at least a portion of the second well region SW and disposed along an edge of the second well region SW);
a third channel region being a portion of the third well region and disposed along an edge of the third well region (TW, 29, annotated Fig. 20, column 16, lines 30-33 describes wherein the surface of the well region 29 comprising the third well region TW functions as a channel region wherein the surface of the third well region TW comprises an edge resulting in a third channel region being at least a portion of the third well region TW and disposed along an edge of the third well region TW);
a first gate portion on the first well region and the first channel region (FG and 18, annotated Fig. 18 and annotated Fig. 20, column 3, lines 59-60 describe a gate electrode 18 wherein annotated Fig. 18 depicts a first gate portion FG as shown disposed above and overlapping the first well region FW in annotated Fig. 20 wherein the first gate portion FG disposed on the first well region FW comprises the first channel region at the edge resulting in the first gate portion FG being disposed on the first channel region);
a second gate portion disposed on the second well region and the second channel region, spaced apart from the first gate portion, and non-overlapped with the first channel region (SG and 18, annotated Fig. 18 and annotated Fig. 20, column 3, lines 59-60 describe the gate electrode 18 wherein annotated Fig. 18 depicts a second gate portion SG as shown disposed above and overlapping the second well region SW in annotated Fig. 20 and therefore disposed on the second channel region disposed along the edge of the second well region SW and wherein the second gate portion SG is spaced apart from the first gate portion FG and non-overlapped with the first channel region of the first well region FW); and
a third gate portion disposed on the first well region and the third well region (TG, FW and TW, annotated Fig. 19, column 3, lines 59-60 describe the gate electrode 18 wherein annotated Fig. 19 depicts a third gate portion TG as shown disposed above and overlapping the first well region FW) and disposed to overlap the first channel region (TG and FW, annotated Fig. 19, column 16, lines 30-33 describes wherein the surface of the well region 29 comprising the first well region FW comprises the first channel region along the surface wherein the third gate region TR is overlapping the edge of the first well region FW and therefore the first channel region) and the third channel region (TG and TW, annotated Fig. 19, column 16, lines 30-33 describes wherein the surface of the well region 29 comprising the third well region TW comprises the third channel region along the surface wherein the third gate region TR is overlapping the edge of the third well region TW and therefore the third channel region).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-7, 13-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuyoshi Oota et al. (US 9,887,285 B1; hereinafter “Oota”) in view of David Raymond Zinn (US 2015/0162431 A1; hereinafter “Zinn”)
Regarding Claim 2, Oota discloses all the limitations of claim 1.
Oota fails to explicitly disclose the semiconductor device of claim 1, further comprising a field insulating film disposed on the substrate and disposed between the first gate portion and the second gate portion.
However, Zinn teaches a similar semiconductor device, further comprising a field insulating film disposed on the substrate (406, Fig. 7, para [0055] describes a field oxide layer 406 disposed on a substrate 402 surrounding a cell region of a device between the field oxide layers 406) and disposed between the first gate portion and the second gate portion (440, FG2 and SG2, annotated Fig. 7, para [0047] describes a dielectric separation structure 440 which may be a field oxide layer of the field insulating film 406 and 440 between a first gate portion FG2 and second gate portion SG2).
PNG
media_image4.png
383
464
media_image4.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Oota with Zinn to further disclose a semiconductor device comprising a field insulating film disposed on the substrate and disposed between the first gate portion and the second gate portion in order to provide the advantage of providing a field oxide insulating film which may reduce the parasitic gate-to-drain overlap capacitance and to maintain a desired separation to avoid pinch-off in the drain drift region (Zinn, para [0047]).
Regarding Claim 3, the combination of Oota and Zinn teaches the semiconductor device of claim 2, further comprising a gate extension portion disposed on the field insulating film (Zinn, GE and 440, annotated Fig. 8 depicts a gate extension portion GE disposed on the field insulating film 440) and disposed between the first gate portion and the second gate portion (Zinn, GE, FG2 and SG2, annotated Fig. 7 and annotated Fig. 8 depicts the gate extension portion GE disposed between the first gate portion FG2 and the second gate portion SG2).
PNG
media_image5.png
301
398
media_image5.png
Greyscale
Regarding Claim 4, the combination of Oota and Zinn teaches the semiconductor device of claim 3, wherein the field insulating film comprises:
a first portion surrounding the cell region (Zinn, 406, Fig. 7, para [0055] describes a first portion of the insulating film 406 disposed on a substrate 402 defining a cell region of a device between the field oxide layers 406 therefore surrounding the cell region); and
a second portion disposed between the first gate portion and the second gate portion (440, FG2 and SG2, annotated Fig. 7, para [0047] describes a second portion 440 of the field insulating film 406 and 440 between a first gate portion FG2 and second gate portion SG2), disposed between the first well region and the second well region (Zinn, 440 and 414, Fig. 7, para [0048] describes the second portion 440 of the field insulating film 406 and 440 disposed between a first well region 414 and a second well region 414 on an opposite side of the second portion 440), and disposed between the third well region and the second well region (Zinn, 440 and 414, Fig. 7 wherein upon combining Oota with Zinn, the second portion 440 of the field insulating film of Zinn may further be disposed between the second well region SW and third well region TW of Oota).
Regarding Claim 5, the combination of Oota and Zinn teaches the semiconductor device of claim 4, wherein the second portion of the field insulating film extends along the first gate portion and the second gate portion (Zinn, 440, FG2 and SG2, annotated Fig. 7 depicts wherein the second portion 440 of the field insulating film extends along side surfaces of the first gate portion FG2 and second gate portion SG2), between the first gate portion and the second gate portion (Zinn, 440, FG2 and SG2, annotated Fig. 7 depicts wherein the second portion 440 of the field insulating film extends between the first gate portion FG2 and second gate portion SG2).
Regarding Claim 6, the combination of Oota and Zinn teaches the semiconductor device of claim 2, further comprising a third gate portion disposed in overlap with a part of the first well region and a part of the third well region (Oota, TG, FW and TW, annotated Fig. 19, column 3, lines 59-60 describe the gate electrode 18 wherein annotated Fig. 19 depicts a third gate portion TG as shown disposed above and overlapping the first well region FW and third well region TW in annotated Fig. 19) and disposed between the first well region and the third well region (Oota, TG, FW and TW, annotated Fig. 19 depicts wherein the third gate portion TG is disposed between the first well region FW and the third well region TW).
PNG
media_image6.png
423
502
media_image6.png
Greyscale
Regarding Claim 7, the combination of Oota and Zinn teaches the semiconductor device of claim 2, further comprising an insulating film disposed on each of the first gate portion, the second gate portion (Oota, 20, FG and SG, annotated Fig. 20, column 12, lines 1-2 describe an interlayer insulating layer 20 disposed on each of the first gate portion FG and second gate portion SG and Zinn teaches in para [0048] an interlayer insulating layer 416 disposed on each of the first gate portion FG2 and second gate portion SG2 as shown in annotated Fig. 7), and the gate extension portion (Zinn, GE and 416, annotated Fig. 8 and Fig. 7 depicts wherein the insulating film 416 is further disposed on the gate extension portion GE as shown in Fig. 7 and annotated Fig. 8).
Regarding Claim 13, Oota discloses all the limitations of claim 12.
Oota fails to explicitly disclose the semiconductor device of claim 1, further comprising a field insulating film disposed on the substrate and disposed between the first gate portion and the second gate portion; and a gate extension portion disposed on the field insulating film and disposed between the first gate portion and the second gate portion.
However, Zinn teaches a similar semiconductor device, further comprising a field insulating film disposed on the substrate (406, Fig. 7, para [0055] describes a field oxide layer 406 disposed on a substrate 402 surrounding a cell region of a device between the field oxide layers 406) and disposed between the first gate portion and the second gate portion (440, FG2 and SG2, annotated Fig. 7, para [0047] describes a dielectric separation structure 440 which may be a field oxide layer of the field insulating film 406 and 440 between a first gate portion FG2 and second gate portion SG2); and
a gate extension portion disposed on the field insulating film (GE and 440, annotated Fig. 8 depicts a gate extension portion GE disposed on the field insulating film 440) and disposed between the first gate portion and the second gate portion (GE, FG2 and SG2, annotated Fig. 7 and annotated Fig. 8 depicts the gate extension portion GE disposed between the first gate portion FG2 and the second gate portion SG2).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Oota with Zinn to further disclose a semiconductor device comprising a field insulating film disposed on the substrate and disposed between the first gate portion and the second gate portion in order to provide the advantage of producing a field oxide insulating film which may provide a larger separation between the planar gate and the semiconductor body in order to reduce the parasitic gate-to-drain overlap capacitance and to maintain a desired separation to avoid pinch-off in the drain drift region (Zinn, para [0047]).
Regarding Claim 14, the combination of Oota and Zinn teaches the semiconductor device of claim 13, wherein the field insulating film comprises:
a first portion surrounding the cell region (Zinn, 406, Fig. 7, para [0055] describes a first portion of the insulating film 406 disposed on a substrate 402 defining a cell region of a device between the field oxide layers 406 therefore surrounding the cell region); and
a second portion disposed between the first gate portion and the second gate portion (Zinn, 440, FG2 and SG2, annotated Fig. 7, para [0047] describes a second portion 440 of the field insulating film 406 and 440 between a first gate portion FG2 and second gate portion SG2), disposed between the first well region and the second well region (Zinn, 440 and 414, Fig. 7, para [0048] describes the second portion 440 of the field insulating film 406 and 440 disposed between a first well region 414 and a second well region 414 on an opposite side of the second portion 440), and disposed between the third well region and the second well region (Zinn, 440 and 414, Fig. 7 wherein upon combining Oota with Zinn, the second portion 440 of the field insulating film of Zinn may further be disposed between the second well region SW and third well region TW of Oota), and
wherein the second portion of the field insulating film extends along the first gate portion and the second gate portion (Zinn, 440, FG2 and SG2, annotated Fig. 7 depicts wherein the second portion 440 of the field insulating film extends along side surfaces of the first gate portion FG2 and second gate portion SG2), between the first gate portion and the second gate portion (Zinn, 440, FG2 and SG2, annotated Fig. 7 depicts wherein the second portion 440 of the field insulating film extends between the first gate portion FG2 and second gate portion SG2).
Regarding Claim 15, the combination of Oota and Zinn teaches the semiconductor device of claim 13, further comprising an insulating film disposed on each of the first gate portion, the second gate portion (Oota, 20, FG and SG, annotated Fig. 20, column 12, lines 1-2 describe an interlayer insulating layer 20 disposed on each of the first gate portion FG and second gate portion SG and Zinn teaches in para [0048] an interlayer insulating layer 416 disposed on each of the first gate portion FG2 and second gate portion SG2 as shown in annotated Fig. 7), and the gate extension portion (Zinn, GE and 416, annotated Fig. 8 and Fig. 7 depicts wherein the insulating film 416 is further disposed on the gate extension portion GE as shown in Fig. 7 and annotated Fig. 8).
Regarding Claim 16, the combination of Oota and Zinn teaches the semiconductor device of claim 13, wherein the third gate portion is disposed to overlap a doped region between the first channel region and the third channel region (Oota, TG, DR and 35C, annotated Fig. 18 II, column 13, lines 29-35 describe a region 35c doped to have a higher impurity concentration that the surrounding region wherein the third gate TG which may extending in a vertical direction perpendicular to the second direction SD is disposed to overlap the doped region in the vertical direction perpendicular to the second direction SD as shown in annotated Fig. 18 II).
PNG
media_image7.png
469
546
media_image7.png
Greyscale
Regarding Claim 18, Oota teaches a semiconductor device comprising:
a substrate comprising a cell region (22, Fig. 19 and Fig. 20, column 3, lines 61-62 describe an n+ type region upon which a drift layer is disposed wherein Fig. 16 and Fig. 17 depict a cell region of the substrate 22);
a first well region in the cell region of the substrate (FW and 29, annotated Fig. 20, column 9, line 57 describes a p-type body region 29 comprising a first well region FW in the cell region of the substrate 22);
a second well region disposed in the cell region and spaced apart from the first well region in a first direction (SW and 29, annotated Fig. 20, column 9, line 57 describes the p-type body region 29 comprising a second well region SW in the cell region of the substrate 22 spaced apart from the first well region FW in a first direction FW);
a first gate portion on the first well region (FG and 18, annotated Fig. 18 and annotated Fig. 20, column 3, lines 59-60 describe a gate electrode 18 wherein annotated Fig. 18 depicts a first gate portion FG as shown disposed on the first well region FW in annotated Fig. 20);
a second gate portion on the second well region (SG and 18, annotated Fig. 18 and annotated Fig. 20, column 3, lines 59-60 describe the gate electrode 18 wherein annotated Fig. 18 depicts a second gate portion SG as shown disposed on the second well region SW in annotated Fig. 20);
Oota fails to explicitly disclose a field insulating film disposed on the substrate and disposed between the first gate portion and the second gate portion; and a gate extension portion disposed on the field insulating film and disposed between the first gate portion and the second gate portion.
However, Zinn teaches a similar semiconductor device, further comprising a field insulating film disposed on the substrate (406, Fig. 7, para [0055] describes a field oxide layer 406 disposed on a substrate 402 surrounding a cell region of a device between the field oxide layers 406) and disposed between the first gate portion and the second gate portion (440, FG2 and SG2, annotated Fig. 7, para [0047] describes a dielectric separation structure 440 which may be a field oxide layer of the field insulating film 406 and 440 between a first gate portion FG2 and second gate portion SG2); and
a gate extension portion disposed on the field insulating film (GE and 440, annotated Fig. 8 depicts a gate extension portion GE disposed on the field insulating film 440) and disposed between the first gate portion and the second gate portion (GE, FG2 and SG2, annotated Fig. 7 and annotated Fig. 8 depicts the gate extension portion GE disposed between the first gate portion FG2 and the second gate portion SG2).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Oota with Zinn to further disclose a semiconductor device comprising a field insulating film disposed on the substrate and disposed between the first gate portion and the second gate portion in order to provide the advantage of producing a field oxide insulating film which may provide a larger separation between the planar gate and the semiconductor body in order to reduce the parasitic gate-to-drain overlap capacitance and to maintain a desired separation to avoid pinch-off in the drain drift region (Zinn, para [0047]).
Regarding Claim 19, the combination of Oota and Zinn teaches the semiconductor device of claim 18, further comprising:
a third well region disposed in the cell region and spaced apart from the first well region along a second direction intersecting the first direction (Oota, 29 and TW, annotated Fig. 17, Fig. 19 and Fig. 20, column 9, line 57 describes the p-type body region 29 comprising a third well TW disposed in the cell region and spaced apart from the first well FW in a second direction SD intersecting the first direction FD as shown in annotated Fig. 17); and
a third gate portion disposed on the first well region and the third well region (Oota, TG, FW and TW, annotated Fig. 19, column 3, lines 59-60 describe the gate electrode 18 wherein annotated Fig. 19 depicts a third gate portion TG as shown disposed above and overlapping the first well region FW).
Regarding Claim 20, the combination of Oota and Zinn teaches the semiconductor device of claim 19, wherein the field insulating film comprises:
a first portion surrounding the cell region (Zinn, 406, Fig. 7, para [0055] describes a first portion of the insulating film 406 disposed on a substrate 402 defining a cell region of a device between the field oxide layers 406 therefore surrounding the cell region); and
a second portion disposed between the first gate portion and the second gate portion (Zinn, 440, FG2 and SG2, annotated Fig. 7, para [0047] describes a second portion 440 of the field insulating film 406 and 440 between a first gate portion FG2 and second gate portion SG2), disposed between the first well region and the second well region (Zinn, 440 and 414, Fig. 7, para [0048] describes the second portion 440 of the field insulating film 406 and 440 disposed between a first well region 414 and a second well region 414 on an opposite side of the second portion 440), and disposed between the third well region and the second well region (Zinn, 440 and 414, Fig. 7 wherein upon combining Oota with Zinn, the second portion 440 of the field insulating film of Zinn may further be disposed between the second well region SW and third well region TW of Oota), and
wherein the second portion of the field insulating film extends along the first gate portion and the second gate portion (Zinn, 440, FG2 and SG2, annotated Fig. 7 depicts wherein the second portion 440 of the field insulating film extends along side surfaces of the first gate portion FG2 and second gate portion SG2), between the first gate portion and the second gate portion (Zinn, 440, FG2 and SG2, annotated Fig. 7 depicts wherein the second portion 440 of the field insulating film extends between the first gate portion FG2 and second gate portion SG2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights