Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 9,508,683 B1).
Regarding independent claim 1: Choi teaches (e.g., Figs. 1-2) a semiconductor package, comprising:
a circuit board (Col. 4, Lines 19-25, Col. 4, Lines 60-62 and Col. 5, Lines 1-2: the package substrate is a printed circuit board (PCB));
semiconductor chips (Col. 4, Lines 19-25 and Col. 4, Lines 60-64; #200) mounted on the circuit board;
a molding (Col. 6, Lines 39-40: #400) formed on the circuit board and covering each of the semiconductor chips (200);
an electromagnetic shield (Col. 6, Lines 58-67 and Col. 7, Lines 1-7: #500) formed on the circuit board and covering the molding; and
ground wires (Col. 7, Lines 1-7: #320) connected to ground pads (Col. 5, Lines 15-28; the second connecting pad 103 may be provided as a ground terminal to which and Col. 7, Lines 1-7; #101 through 104), which are installed on the circuit board,
wherein the ground wires (320) penetrate the molding (400) and the electromagnetic shield (Fig. 2; #500).
Regarding claim 3: Choi teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends,
wherein the electromagnetic shield (500) exposes side surface of the molding (400).
Regarding claim 4: Choi teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends,
wherein the ground wires include first portions (lower portion of 320) and second portions (upper portion of 320),
the molding (400) envelops the first portions (lower portion of 320), and the electromagnetic shield (500) envelops the second portions (upper portion of 320).
Regarding claim 5: Choi teaches the claim limitation of the semiconductor package of claim 4, on which this claim depends,
wherein the first portions (lower portion of 320) contact an upper surface of the circuit board (100), and the second portions (upper portion of 320) contact side surface of the molding (400).
Regarding claim 6: Choi teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends,
wherein the molding (400) has a first upper surface (lower side surface), a
second upper surface (top surface), which is higher than the first upper surface (Fig. 2; top surface higher than intermediate side surface), and inclined surfaces (intermediate side surface), which connect the first and second upper surfaces (lower side surface and top surface) to one another.
Regarding claim 7: Choi teaches the claim limitation of the semiconductor package of claim 6, on which this claim depends,
wherein a first angle formed between the inclined surfaces and an imaginary extension of the first upper surface is an acute angle (Fig. 2; inclined surfaces and an imaginary extension of the lower side surface is an acute angle).
Regarding claim 8: Choi teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends,
wherein on side surface of the semiconductor package (Col. 9, Lines 39-50: 10), the circuit board (100) and the electromagnetic shield (500), including the ground wires (320), are sequentially stacked (Fig. 2).
Regarding claim 9: Choi teaches the claim limitation of the semiconductor package of claim 8, on which this claim depends,
wherein side surface of the circuit board (100), first surfaces of the ground wires (320), exposed from the electromagnetic shield (500), and side surface of the electromagnetic shield (500) lie in common planes (Figs. 1-2; horizontal plane).
Regarding claim 10: Choi teaches the claim limitation of the semiconductor package of claim 8, on which this claim depends,
wherein the molding (400) is interposed between the circuit board (100) and the electromagnetic shield (500).
Regarding claim 11: Choi teaches the claim limitation of the semiconductor package of claim 10, on which this claim depends,
wherein side surface of the circuit board (100), side surface of the molding (400), first surfaces of the ground wires (320), exposed from the electromagnetic shield (500), and side surface of the electromagnetic shield (500) lie in common planes (Figs.1-2; horizontal plane).
Regarding claim 12: Choi teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends,
wherein the molding includes a groove, which is formed at opposite ends of the molding (Fig. 2; molding 400 includes groove at its ends), parts of the ground wires (320) are positioned in the groove, and the electromagnetic shield (500) fills the groove and covers the parts of the ground wires (320) positioned in the groove.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 9,508,683 B1) in view of Dias et al. (US 2017/0287846 A1).
Regarding claim 2: Choi teaches the claim limitation of the semiconductor package of claim 1, on which this claim depends,
wherein the ground wires (320) are on side surface of the electromagnetic shield (500).
Choi does not expressly teach that the ground wires are exposed from side surface of the electromagnetic shield.
Dias teaches (e.g., Figs. 4A-4B) a semiconductor package comprising ground wires ([0041]-[0042]: 426) exposed from side surface of an electromagnetic shield ([0041]: 222).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Choi, the ground wires being exposed from side surface of the electromagnetic shield, as taught by Dias, for the benefits of reducing EMI emissions, improving signal integrity, minimizing noise.
Regarding independent claim 13: Choi teaches (e.g., Figs. 1-2) a semiconductor package, comprising:
a circuit board (Col. 4, Lines 19-25, Col. 4, Lines 60-62 and Col. 5, Lines 1-2: the package substrate is a printed circuit board (PCB)) including a center area and a peripheral area (Fig. 2);
semiconductor chips (Col. 4, Lines 19-25 and Col. 4, Lines 60-64; #200) mounted on the center area (Fig. 2);
a molding (Col. 6, Lines 39-40: #400) formed on the circuit board, covering each of the semiconductor chips, and including a groove, which is formed at opposite ends of the molding (Fig. 2; grooves at the sides);
an electromagnetic shield (Col. 6, Lines 58-67 and Col. 7, Lines 1-7: #500) formed on the circuit board, filling the groove, and covering an upper surface of the molding (400); and
ground wires (Col. 7, Lines 1-7: #320) installed in the peripheral area and connected to ground pads (Col. 5, Lines 15-28; the second connecting pad 103 may be provided as a ground terminal to which and Col. 7, Lines 1-7; #101 through 104), which are installed on the circuit board (100), the ground wires (320) including
first portions (lower portion), which penetrate the molding, and
second portions (upper portion), which penetrate parts of the electromagnetic shield (500) formed in the groove.
Choi does not expressly teach that the electromagnetic shield exposes the second portions.
Dias teaches (e.g., Figs. 4A-4B) a semiconductor package comprising ground wires ([0041]-[0042]: 426) a second portion (upper portion) and an electromagnetic shield ([0041]: 222).
Dias further teaches that the electromagnetic shield ([0041]: 222) exposes the second portions ([0041]-[0042]: upper portions of ground wires 426).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Choi, the electromagnetic shield exposing the second portions, as taught by Dias, for the benefits of reducing EMI emissions, improving signal integrity, minimizing noise.
Regarding claim 14: Choi and Dias teach the claim limitation if the semiconductor package of claim 13, on which hit claim depends.
Choi as modified Dias teaches that the second portions of the ground wires (Choi: upper portions of 320) are exposed on side surface of the electromagnetic shield (Choi: 500).
Regarding claim 15: Choi and Dias teach the claim limitation if the semiconductor package of claim 13, on which hit claim depends, wherein
the first portions (Choi: lower portions of 320) contact an upper surface of the circuit board (100), and the second potions (Choi: upper portions of 320) contact side surface of the electromagnetic shield (Choi: 500).
Regarding claim 16: Choi and Dias teach the claim limitation if the semiconductor package of claim 15, on which hit claim depends, wherein
the molding (Choi: 400) has a first upper surface (Choi: lower portion of the inclined portion of 400), which is positioned in the groove, and
the second portions of the ground wires (Choi: upper portions of 320) overlap with the first upper surface (Choi: Fig. 2; lower portion of the inclined portion of 400) and an upper surface of the circuit board (Choi: 100) in a vertical direction.
Regarding claim 17: Choi and Dias teach the claim limitation if the semiconductor package of claim 16, on which hit claim depends,
wherein the molding has a first upper surface (Choi: Fig. 2; lower portion of the inclined portion of 400), a second upper surface (Choi: Fig. 2; upper portion of the inclined portion of 400), which is higher than the first upper surface (Choi: Fig. 2), and inclined surfaces (Choi: Fig. 2; inclined portion of 400), which connect the first and second upper surfaces to one another, and
a first angle formed between the inclined surfaces (Choi: Fig. 2; inclined portion of 400) and an imaginary extension of the first upper surface (Choi: Fig. 2; lower portion of inclined portion of 400) is an acute angle (Choi: Fig. 2).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 9,508,683 B1) in view of Kwak et al. (US 2008/0272469 A1) and Dias et al. (US 2017/0287846 A1).
Regarding independent claim 18: Choi teaches (e.g., Figs. 1-2) a method of fabricating a semiconductor package, comprising:
providing a circuit board Col. 4, Lines 19-25, Col. 4, Lines 60-62 and Col. 5, Lines 1-2: the package substrate is a printed circuit board (PCB)), which extends in a first direction (horizontal direction),
first semiconductor chips (Col. 4, Lines 19-25 and Col. 4, Lines 60-64; #200), which are disposed on the circuit board, which are spaced apart from the first semiconductor chips in the first direction, on the circuit board (100), and
ground wires (Col. 7, Lines 1-7: #320), which are connected to ground pads (Col. 5, Lines 15-28; the second connecting pad 103 may be provided as a ground terminal to which and Col. 7, Lines 1-7; #101 through 104) that are installed on the circuit board (100);
forming a molding (Col. 6, Lines 39-40: #400), which is formed on the circuit board (100) and covers the first semiconductor chips (200), the second semiconductor chips, and the ground wires (320).
Choi does not expressly teach
forming second semiconductor chips, which are spaced apart from the first semiconductor chips in the first direction,
forming a groove, which is positioned at opposite ends of the molding, between the first semiconductor chips and the second semiconductor chips, in the molding through a laser drilling process,
the groove exposing the ground wires; and forming an electromagnetic shield, which covers an upper surface of the molding, fills the groove, and envelops the ground wires in the groove.
Kwak teaches (e.g., Figs 3A-3E) a method of fabricating a semiconductor package, comprising:
forming second semiconductor chips ([0031]: two rightmost semiconductor chips 320), which are spaced apart from the first semiconductor chips ([0031]: two leftmost semiconductor chips 320) in a first direction (horizontal direction);
forming a groove (Fig. 3D; element 301), which is positioned at opposite ends of a molding ([0031]: 330), between the first semiconductor chips and the second semiconductor chips (leftmost semiconductor chips 320 and rightmost semiconductor chips respectively), in the molding through (300),
the groove (300) exposing the ground wires ([0031]-[0033], [0035]: 313; wires 313 are capable of being used as ground wires); and
forming an electromagnetic shield ([0022]-[0023]: “The molding 150 may include electromagnetic shielding material” and “the conductive layer 140 can ground EMI coming into/out of the semiconductor die package 100 through the ground terminals 112a and 112b”; thus indicating that 340 is an electromagnetic shield; [0031]-[0032], [0049]-[0050] : 340), which covers an upper surface of the molding (330), fills the groove (301), and envelops the ground wires (313) in the groove.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Choi, the method of
forming second semiconductor chips, which are spaced apart from the first semiconductor chips in the first direction, forming a groove, which is positioned at opposite ends of the molding, between the first semiconductor chips and the second semiconductor chips, in the molding through a laser drilling process, the groove exposing the ground wires; and forming an electromagnetic shield, which covers an upper surface of the molding, fills the groove, and envelops the ground wires in the groove, as taught by Kwak, for the befits of reducing electromagnetic radiation interferences between the groups of functional chips and thus improve device reliability.
Dias teaches a method (e.g., Figs. 1A-1F) comprising a laser drilling process ([0015], [0017] and [0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Choi as modified by Kwak, the method of laser drilling process, as taught by Dias, for the benefits of improving the unidirectional trench formation, and at the same time increasing the drilling process speed.
Regarding claim 19: Choi, Kwak and Dias teach the claim limitation if the method of claim 18, on which hit claim depends,
Choi as modified by Kwak and Dias teaches that in a cross-sectional view of the ground wires, taken in a direction perpendicular to an upper surface of the circuit board, sequentially stacking the circuit board (Choi: 100), the molding (Choi: 400), and the electromagnetic shield (Choi: 500), including the ground wires (Choi: 320).
Regarding claim 20: Choi and Dias teach the claim limitation if the method of claim 18, on which hit claim depends,
Choi as modified by Kwak and Dias teaches that side surface of the molding (Choi: 400), first surfaces of the ground wires (Choi: 320), exposed from the electromagnetic shield (Choi: 500), and side surface of the electromagnetic shield (Choi: 500) lie in common planes (horizontal plane).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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