Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant's election without traverse of Group I, claims 1-13, drawn to memory device with configuration bits and redundant bits, in the reply filed on 02/17/2026 is acknowledged. Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to non-elected inventions.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-8 are rejected under 35 U.S.C. l12(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites “each of the first, second, and third inputs” where the scope related to said limitation is deemed indefinite. Because, the limitation would be interpreted as “the first inputs” or “the second inputs” or “the third inputs” which clearly indicate multiple first, second or third inputs but the previous limitation indicate only single (not plural) input. So, the limitation is unclear and deemed indefinite.
Claim 1 also recites “a third input” and “third inputs” in line 7 and “the third input” in line 9 where the scope related to said limitations are deemed indefinite. Because, it is not clear where a single third input and multiple (plural) third inputs are not same and overall scope is unclear.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Fackenthal (US Pub # 2020/0059252).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Fackenthal teaches a memory device comprising: a first configuration bit group including a plurality of bits, the plurality of bits including: a plurality of configuration bits; at least one redundant configuration bit (see Fig. 1-4, 10-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110, 0113-0139, 0142-0159, memory configuration 400 includes configuration bits group, data group, codeword, control group); a plurality of configuration bit multiplexers each configured to receive (i) a first input from a first bit in the plurality of bits and/or a second input from a second bit in the plurality of bits and (ii) a third input from a decoder, each of the first, second, and third inputs indicating a respective logical state (see Fig. 1-4, 10-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110, 0113-0139, 0142-0159, where 205, 210, 215, 220 are the input bits), wherein the logical state includes a first state or a second state; and wherein, based on the logical state of the third input received from the decoder, each configuration bit multiplexer is configured to output: the logical state of the first input from the first bit, or the logical state of the second input from the second bit (see Fig. 1-4, 10-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110, 0113-0139, 0142-0159, unit 245, 260, 265 includes multiplexer, unit 120, 130 are decoder).
Even though Fackenthal teaches input bits has logical state but silent exclusively about the logical state includes a first state or a second state. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Fackenthal where data, codeword, control bits have original state or inverted state i.e. first or second state (see paragraph 0055, 0065, 0067) in order to decrease number of errors during reading and to increase reliability of memory device (see paragraph 0017).
Regarding claim 2, Fackenthal teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Fackenthal further teaches, wherein, when one of the plurality of configuration bits is faulty, at least one of the plurality of configuration bit multiplexers receives the second input from the second bit in the plurality of bits (see Fig. 1-4, 7-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110, 0113-0139, 0142-0159).
Regarding claim 3, Fackenthal teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Fackenthal further teaches, wherein, when one of the plurality of configuration bits is faulty, at least one of the plurality of configuration bit multiplexers receives the second input from the second bit in the plurality of bits, the second bit being the at least one redundant configuration bit (see Fig. 1-4, 7-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110, 0113).
Regarding claim 4, Fackenthal teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Fackenthal further teaches, wherein the decoder is configured to selectively program the third input provided to each configuration bit multiplexer based on whether and/or where a faulty configuration bit exists (see Fig. 1-4, 7-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110).
Regarding claim 5, Fackenthal teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Fackenthal further teaches, further comprising at least one redundant configuration bit multiplexer configured to receive an input from the at least one redundant configuration bit (see Fig. 1-4, 7-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110, 0113-0139).
Regarding claim 6, Fackenthal teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Fackenthal further teaches, further comprising a scan chain electrically connected to the plurality of bits and configured to test an output of each bit in the plurality of bits to determine any faulty bit (see Fig. 1-4, 7-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110, 0113-0135).
Regarding claim 7, Fackenthal teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Fackenthal further teaches, wherein the each bit in the plurality of bits is one of a toggle magnetoresistive random access memory (MRAM), a spin orbit torque (SOT) MRAM, a spin transfer torque (STT) MRAM, or a voltage-controlled magnetic anisotropy (VCMA) MRAM (see Fig. 1-4, 7-11 and paragraph 0003, 0015-0031).
Regarding claim 8, Fackenthal teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Fackenthal further teaches, further comprising: a second configuration bit group substantially identical to the first configuration bit group; and a configuration bit group multiplexer including: a select input, a first output to an input of the first configuration bit group, and a second output to an input of the second configuration bit group, wherein, based on a logical state of the select input to the configuration bit group multiplexer, the configuration bit group multiplexer is configured to selectively access one of the first configuration bit group or the second configuration bit group (see Fig. 1-4, 7-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110, 0113-0139, 0142-0150).
Regarding independent claim 9, Fackenthal teaches a memory device comprising: a plurality of configuration bits; an inversion bit, each of the plurality of configuration bits and the inversion bit having a respective logical state (see Fig. 1-4, 10-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110, 0113-0139, 0142-0159, memory configuration 400 includes data, codeword, control bits), wherein the logical state includes a first state or a second state; and an exclusive OR (XOR) tree circuit configured to receive an input from each of the plurality of configuration bits and the inversion bit (see Fig. 1-4, 10-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110, 0113-0139, 0142-0159, unit 255 includes XOR circuit, see specially paragraph 0059-0060) and: if the inversion bit includes the first state, output the logical state of each corresponding configuration bit in the plurality of configuration bits, or if the inversion bit includes the second state, invert the logical state of each corresponding configuration bit in the plurality of configuration bits (see Fig. 1-4, 10-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110, 0113-0139, 0142-0159, 220 inversion bits, unit bit flipper 255 invert bits).
Even though Fackenthal teaches input bits has logical state but silent exclusively about the logical state includes a first state or a second state. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Fackenthal where data, codeword, control bits have original state or inverted state i.e. first or second state (see paragraph 0055, 0065, 0067) in order to decrease number of errors during reading and to increase reliability of memory device (see paragraph 0017).
Regarding claim 10, Fackenthal teaches all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Fackenthal further teaches, wherein the inversion bit includes a plurality of inversion bits, and wherein the memory device further comprises: a triple modular redundancy (TMR) circuit configured to determine the logical state of the inversion bit by performing a majority voting based on the logical states of the plurality of inversion bits and output the determined logical state of the inversion bit to the XOR tree circuit (see Fig. 1-4, 7-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110, 0113-0139, 0142-0155).
Regarding claim 11, Fackenthal teaches all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Fackenthal further teaches, wherein the output of each configuration bit in the plurality of configuration bits is stored in a first portion of non-volatile memory having an address and is configured to be output by the XOR tree circuit, wherein the address is selectively stored in a second portion of the non-volatile memory when the inversion bit is fixed at the first state or the second state, and wherein the logical state of each configuration bit in the plurality of configuration bits is inverted when the address is stored in the second portion of non-volatile memory (see Fig. 1-4, 7-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096, 0099-0110, 0113-0139).
Regarding claim 12, Fackenthal teaches all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Fackenthal further teaches, wherein the each configuration bit in the plurality of configuration bits is one of a toggle magnetoresistive random access memory (MRAM), a spin orbit torque (SOT) MRAM, a spin transfer torque (STT) MRAM, or a voltage-controlled magnetic anisotropy (VCMA) MRAM (see Fig. 1-4, 7-11 and paragraph 0003, 0015-0031).
Regarding claim 13, Fackenthal teaches all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Fackenthal further teaches, wherein the plurality of configuration bits includes at least four configuration bits (see Fig. 1-4, 7-11 and paragraph 0015-0031, 0037-0059, 0063-0069, 0075-0096).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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