DETAILED ACTION
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/11/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 11-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ueda (US 2012/0273922).
As for claim 1, Ueda discloses in Figs. 1-11 and the related text a semiconductor memory device comprising:
a substrate 1 which comprises a cell (right) area, a peripheral (left) area defined around the cell area, and a boundary (middle) area between the cell area and the peripheral area (Fig. 2), wherein the cell area comprises an active area defined by an element isolation layer 2 (fig. 2);
a storage pad 17 connected to the active area in the cell area (Fig. 2);
a capacitor 27 which comprises a lower electrode 24 connected to the storage pad, a first electrode support layer (right 21) supporting the lower electrode, a capacitor dielectric layer 25 extending along the lower electrode, and an upper electrode 26 on the capacitor dielectric layer (fig. 2);
a peripheral gate 5 on the peripheral area of the substrate (Fig. 2);
first peripheral contact plugs 31 on both sides of the peripheral gate, the first peripheral contact plugs being connected to the substrate (fig. 2);
a first interlayer insulating layer 19 on the storage pad and the first peripheral contact plugs (Fig. 2), a first peripheral wiring line 18 being formed in the first interlayer insulating layer (Fig. 2);
a second interlayer insulating layer 20 on the first interlayer insulating layer, a second peripheral contact plug (low portion of 35) connected to the first peripheral wiring line being formed in the second interlayer insulating layer (Fig. 2); and
a first insulating layer (left 21) on the second interlayer insulating layer, a second peripheral wiring line (middle portion 35) being formed in the first insulating layer, wherein the first insulating layer extends on the boundary area of the substrate such that a sidewall of the first insulating layer contacts the upper electrode (fig. 2), and a height of (a portion of) the first insulating layer (left 21) is equal to or less than a height of the first electrode support layer (right 21) (Fig. 2).
As for claim 2, Ueda discloses the semiconductor memory device of claim 1, wherein a height of (a portion of) the second peripheral wiring line (middle portion of 35) is equal to or less than the height of the first electrode support layer (right 21) (Fig. 2).
As for claim 3, Ueda discloses the semiconductor memory device of claim 1, further comprising an upper contact plug (upper portion of 35) on the first insulating layer on the peripheral area, and the upper contact plug (upper portion of 35) being connected to the second peripheral wiring line (middle portion of 35) (Fig. 2).
As for claim 4, Ueda discloses the semiconductor memory device of claim 3, wherein a lower surface of the upper contact plug (upper portion of 35) is at the same height as an upper surface of the first electrode support layer (right 21) (Fig. 2).
As for claim 5, Ueda discloses the semiconductor memory device of claim 1, further comprising a barrier structure 12/23 on the boundary area of the substrate (Fig. 2).
As for claim 6, Ueda discloses the semiconductor memory device of claim 5, wherein the barrier structure 12 comprises a metal [0067].
As for claim 7, Ueda discloses the semiconductor memory device of claim 5, wherein the barrier structure 23 comprises the same material as the first electrode support layer 21 ([0077] and [0081]).
As for claim 8, Ueda discloses the semiconductor memory device of claim 1, wherein (lower surface of) the first insulating layer (left 21) on the peripheral area is at a lower height than the first electrode support layer (right 21), and (lower surface of) the second peripheral wiring line (middle portion of 35) is at a lower height than the first electrode support layer (Fig. 2).
As for claim 11, Ueda discloses in Figs. 1-11 and the related text a semiconductor memory device comprising:
a substrate which comprises a cell (right) area, a peripheral (left) area defined around the cell area, and a boundary (middle) area between the cell area and the peripheral area (Fig. 2), wherein the cell area comprises an active area defined by an element isolation layer 2 (Fig. 2);
a storage pad 17 connected to the active area in the cell area (Fig. 2);
a capacitor 27 which comprises a lower electrode 24 connected to the storage pad, the lower electrode 24 extending perpendicular to the substrate (Fig. 2), and an electrode support structure 21/23 supporting the lower electrode, wherein the electrode support structure comprises a first electrode support layer 21 and a second electrode support layer 23 on the first electrode support layer;
a peripheral gate 5 on the peripheral area of the substrate (Fig. 2);
first peripheral contact plugs 31 on both sides of the peripheral gate, the first peripheral contact plugs being connected to the substrate (Fig. 2);
a first interlayer insulating layer 16/19 on the storage pad and the first peripheral contact plugs (Fig. 2), a first peripheral wiring line 32/18 being formed in the first interlayer insulating layer;
a second interlayer insulating layer 20 on the first interlayer insulating layer, a second peripheral contact plug (lower portion of right 35) connected to the first peripheral wiring line being formed in the second interlayer insulating layer (Fig. 2);
a first insulating layer 22 on the second interlayer insulating layer, a second peripheral wiring line (upper portion of right 35) being formed in the first insulating layer 22; and
a third peripheral contact plug (left 35) on the first insulating layer of the peripheral area, the third peripheral contact plug being (electrically/thermally) connected to the second peripheral wiring line (Fig. 2), wherein a height of (a portion of) the first insulating layer on the boundary area is equal to or less than a height of the first electrode support layer 21, a height of the first insulating layer 22 on the peripheral area is equal to or less than the height of the first insulating layer 22 on the boundary area (Fig. 2), and a lower surface of the third peripheral contact plug (left 35) (electrically/thermally) contacts an upper surface of the first insulating layer 22 on the peripheral area (Fig. 2).
As for claim 12, Ueda discloses the semiconductor memory device of claim 11, wherein the first electrode support layer 21, (a portion of) the first insulating layer 22 on the boundary area, and (a portion of) the first insulating layer 22 on the peripheral area are at the same height.
As for claim 13, Ueda discloses the semiconductor memory device of claim 11, wherein the second peripheral wiring line 18/32 and (a portion of) the first electrode support layer are at the same height.
As for claim 14, Ueda discloses the semiconductor memory device of claim 11, wherein the lower surface of the third peripheral contact plug (left 35) is at a lower height than the upper surface of the first insulating layer 21 of the boundary area (Fig. 2).
As for claim 15, Ueda discloses the semiconductor memory device of claim 11, wherein the capacitor further comprises: a capacitor dielectric layer 25 extending along a profile of the lower electrode 24 and upper and lower surfaces of each of the first and second electrode support layers (Fig. 2); and an upper electrode 26 disposed on the capacitor dielectric layer (Fig. 2).
As for claim 16, Ueda discloses the semiconductor memory device of claim 15, further comprising a barrier structure between the upper electrode and the second interlayer insulating layer on the boundary area of the substrate, wherein the barrier structure comprises a metal.
As for claim 17, Ueda discloses the semiconductor memory device of claim 15, further comprising a barrier structure (upper portion of 23) between the upper electrode 26 and the second interlayer insulating layer 22 on the boundary area of the substrate (fig. 2), wherein the barrier structure (upper portion of 23) comprises the same material as the first insulating layer of the boundary area [0081].
As for claim 18, Ueda discloses the semiconductor memory device of claim 17, wherein a width of the barrier structure (upper portion of 23) in a horizontal direction is greater than a thickness of (a portion of) the first insulating layer on the boundary area in a vertical direction (Fig. 2).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10 and 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ueda in view of Shin (US 9,431,324).
As for claim 10, Ueda discloses the semiconductor memory device of claim 1, wherein the first electrode support layer 21 comprises silicon nitride film [0077] and the first insulating layer 22 comprise silicon nitride [0080], the first interlayer insulating layer 19 comprises nitride [0073], and the second interlayer insulating layer 20 comprises oxide [0075].
Ueda does not disclose the first electrode support layer and the first insulating layer comprise carbonitride.
Shin teach Figs. 1-2 and the related text an electrode support layer (left 730) and an first insulating layer (right 730) comprises carbonitride (Col. 13 lines 27-31).
Ueda and Shin are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ueda because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Ueda to include the limitations as taught by Shin, in order to suitable insulating materials.
As for claim 20, Ueda discloses in Figs. 1-11 and the related text a semiconductor memory device comprising:
a substrate 1 which comprises a cell (right) area and a peripheral (left) area defined around the cell area, wherein the cell area comprises an active area defined by an element isolation layer 2;
a cell isolation layer 2 in the substrate to define the cell area (Fig. 2);
a bit line 13 on the cell area of the substrate, the bit line comprising a cell conductive line 13 and a cell line capping layer 14 on the cell conductive line;
a cell gate electrode 5/6/7 in the cell area of the substrate,
a storage pad 17 on a side surface of the bit line, the storage pad being connected to the active area in the cell area (Fig. 2);
a capacitor 27 which comprises a lower electrode 24 connected to the storage pad, an electrode support layer supporting (right 21) the lower electrode, a capacitor dielectric layer 25 extending along a profile of the lower electrode and upper and lower surfaces of the electrode support layer, and an upper electrode on the capacitor dielectric layer (Fig. 2);
a peripheral gate 5/6/7 on the peripheral area of the substrate (Fig. 2);
first peripheral contact plugs 31 on both sides of the peripheral gate, the first peripheral contact plugs being connected to the substrate (Fig. 2);
a first interlayer insulating layer 19 on the storage pad and the first peripheral contact plugs, a first peripheral wiring line 18 being formed in the first interlayer insulating layer (Fig. 2);
a second interlayer insulating layer 20 on the first interlayer insulating layer 20 (Fig. 2), a second peripheral contact plug (lower portion of 35) connected to the first peripheral wiring line being formed in the second interlayer insulating layer (fig. 2); and
a first insulating layer (left 21) on the second interlayer insulating layer 20, a second peripheral wiring line (middle portion of 35) being formed in the first insulating layer (Fig. 2), wherein at least a portion of each of the second interlayer insulating layer 20 and the first insulating layer (left 21) extends on the cell isolation layer (Fig. 2), wherein the electrode support layer (right 21) and the first insulating layer (left 21) are at the same height (Fig. 2), and wherein each of the electrode support layer (right 21) and the first insulating layer (left 21) comprises silicon nitride [0077].
Ueda do not teach the cell gate electrode crossing the cell conductive line; and each of the electrode support layer and the first insulating layer comprises carbonitride.
Shin teach Figs. 1-2 and the related text the cell gate electrode crossing the cell conductive line (Fig. 1-2); each of an electrode support layer (left 730) and an first insulating layer (right 730) comprises carbonitride (Col. 13 lines 27-31).
Ueda and Shin are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ueda because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Ueda to include the limitations as taught by Shin, in order to suitable insulating materials.
Allowable Subject Matter
Claim 9 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: “the first insulating layer on the peripheral area is at a lower height than the first insulating layer on the boundary area, and the first insulating layer on the peripheral area comprises a different material from the first insulating layer on the boundary area” as recited in claim 9; and “third interlayer insulating layer on the second interlayer insulating layer, the third peripheral contact plug being formed in the third interlayer insulating layer; a second insulating layer on the third interlayer insulating layer, a third peripheral wiring line 30 connected to the third peripheral contact plug being formed in the second insulating layer; a fourth interlayer insulating layer on the second insulating layer, a fourth peripheral contact plug connected to the third peripheral wiring line being formed in the fourth interlayer insulating layer; and a third insulating layer on the fourth interlayer insulating layer, a fourth peripheral wiring line connected to the fourth peripheral contact plug being formed in the third insulating layer, wherein the electrode support structure further comprises a third electrode support layer on the second electrode support layer, wherein the second electrode support layer, the second insulating layer of the boundary area and the second insulating layer of the peripheral area are at the same height, and wherein the third electrode support layer, the third insulating layer of the boundary area and the third insulating layer of the peripheral area are at the same height” as recited in claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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