Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 11th, 2024, was filed prior to the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9, 11, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (2022/0045008 A1; hereinafter Kang).
Regarding Claim 1, Kang (fig. 1) teaches a semiconductor package ([0016], 1) comprising:
a ceramic substrate ([0017], 110) having a cavity ([0018], CA);
a lower redistribution structure ([0017], 140) on a lower surface of the ceramic substrate (bottom of 110) and electrically connected to the ceramic substrate (110);
an upper redistribution structure ([0017], 130) on an upper surface of the ceramic substrate (top of 110) and electrically connected to the ceramic substrate (110);
a plurality of semiconductor chips ([0016], 200, 300) arranged in a first direction (up and down, see fig. 1) on the upper redistribution structure (130); and
a bridge chip structure ([0017], 120) in the cavity (CA) of the ceramic substrate (110) and comprising a bridge chip (120) electrically connecting the plurality of semiconductor chips (200, 300) to each other.
Regarding Claim 2, Kang (fig. 1) teaches the semiconductor package of claim 1, wherein the bridge chip structure (120) further comprises a bridge pillar ([0024], vertical portions of 124, referred to as bridge pillar, see annotated fig. 2) and an upper bridge pad (horizontal portions of 124, referred to as upper bridge pad, see annotated fig. 2) that electrically connect the bridge chip (120) and the plurality of semiconductor chips (200, 300) to each other.
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Annotated Figure 2
Regarding Claim 3, Kang (fig. 1) teaches the semiconductor package of claim 2, wherein the bridge chip (120) comprises a through silicon via (TSV) ([0025], 126) extending through the bridge chip (120) to the ceramic substrate (110).
Regarding Claim 4, Kang (fig. 1) teaches the semiconductor package of claim 3, wherein the bridge chip structure (120) further comprises a lower bridge pad ([0026], 127) connected to the TSV (126) of the bridge chip (120).
Regarding Claim 5, Kang (fig. 1) teaches the semiconductor package of claim 1, further comprising an encapsulation layer ([0031], 113) that encapsulates the bridge chip structure (120) within the cavity (CA).
Regarding Claim 6, Kang (fig. 1) teaches the semiconductor package of claim 5, wherein the encapsulation layer (113) comprises ceramic material, resin ([0031]), or a combination thereof.
Regarding Claim 9, Kang (fig. 1) teaches the semiconductor package of claim 1, wherein the plurality of semiconductor chips (200, 300) comprise logic semiconductor chips or memory semiconductor chips ([0035]).
Regarding Claim 11, Kang (fig. 1) teaches a semiconductor package comprising:
a ceramic substrate ([0017], 110) having a cavity ([0018], CA),
the ceramic substrate (110) comprising a plurality of first insulating layers ([0019], 112), and
a first circuit wiring layer ([0019], 114) between the plurality of first insulating layers (112);
a lower redistribution structure ([0017], 140) on a lower surface of the ceramic substrate (bottom surface of 110),
the lower redistribution structure (140) comprising a plurality of second insulating layers ([0033], 142) and
a second circuit wiring layer ([0033], 144) between the plurality of second insulating layers (142) and electrically connected to the first circuit wiring layer (114);
an upper redistribution structure ([0019], 130) on an upper surface of the ceramic substrate (top of 110),
the upper redistribution structure (130) comprising a plurality of third insulating layers ([0033], 132) and
a third circuit wiring layer ([0033], 134) between the plurality of third insulating layers (132) and electrically connected to the first circuit wiring layer (114);
a plurality of semiconductor chips ([0016], 200, 300) arranged in a first direction (up and down, see fig. 1) on the upper redistribution structure (130);
a bridge chip structure ([0017], 120) in the cavity (CA) of the ceramic substrate (110) and comprising a bridge chip (120) electrically connecting the plurality of semiconductor chips (200, 300) to each other; and
an encapsulation layer ([0031], 113) encapsulating the bridge chip structure (120) within the cavity (CA), wherein the encapsulation layer (113) comprises ceramic material, resin ([0031]), or a combination thereof.
Regarding Claim 17, Kang (fig. 1) teaches the semiconductor package of claim 11, wherein an upper surface of the encapsulation layer (top of 113) and the top surface of the ceramic substrate (top of 110) are co-planar (see fig. 15).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 7 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kang as applied to Claims 1 and 11 above, and further in view of Qian et al. (2020/0243448 A1; hereinafter Qian).
Regarding Claim 7, Kang doesn’t teach the semiconductor package of claim 1, wherein a depth of the cavity into the ceramic substrate is in a range of about 80 μm to about 200 μm.
However, Qian (fig. 2) teaches a depth of the cavity ([0040], cavity where 212 is formed) into the ceramic substrate ([0039]-[0041], 204, 210, 220) is in a range of about 80 μm to about 200 μm ([0068], cavity made for the bridge die ranges from 25 μm to 400 μm). Depths, however, will not support the patentability of the subject matter encompassed by the prior art unless there is evidence indicating such depths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality of the claimed depth, and similar depths are used for embedded bridge dies in the art, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select the appropriate depth for an embedded bridge die.
Regarding Claim 12, Kang doesn’t teach the semiconductor package of claim 11, wherein a depth of the cavity into the ceramic substrate is in a range of about 80 μm to about 200 μm.
However, Qian (fig. 2) teaches a depth of the cavity ([0040], cavity where 212 is formed) into the ceramic substrate ([0039]-[0041], 204, 210, 220) is in a range of about 80 μm to about 200 μm ([0068], cavity made for the bridge die ranges from 25 μm to 400 μm). Depths, however, will not support the patentability of the subject matter encompassed by the prior art unless there is evidence indicating such depths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality of the claimed depth, and similar depths are used for embedded bridge dies in the art, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select the appropriate depth for an embedded bridge die.
Claims 8 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kang as applied to Claims 1 and 11 above, and further in view of Suk et al. (2022/0157810 A1; hereinafter Suk).
Regarding Claim 8, Kang doesn’t teach the semiconductor package of claim 1, further comprising a capacitor structure at an interface between the ceramic substrate and the upper redistribution structure, wherein the capacitor structure is between a first one of the plurality of semiconductor chips and the ceramic substrate.
However, Suk (fig. 1B) teaches a capacitor structure ([0044], 300) at an interface between the ceramic substrate ([0044], 100) and the upper redistribution structure ([0042], [0065], 151, 153, 410), wherein the capacitor structure (300) is between a first one of the plurality of semiconductor chips ([0044], 210) and the ceramic substrate (100). Suk also teaches this improves power integrity properties ([0058]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor package of Kang to include the capacitor of Suk to improve power integrity properties.
Regarding Claim 13, Kang doesn’t teach the semiconductor package of claim 11, further comprising a capacitor structure at an interface between the ceramic substrate and the upper redistribution structure, wherein the capacitor structure comprises a lower electrode layer on the upper surface of the ceramic substrate, a dielectric layer on an upper surface of the lower electrode layer, and an upper electrode layer on an upper surface of the dielectric layer.
However, Suk (fig. 1B) teaches a capacitor structure ([0044], 300) at an interface between the ceramic substrate ([0044], 100) and the upper redistribution structure ([0042], [0065], 151, 153, 410), wherein the capacitor structure (300) comprises a lower electrode layer ([0044], 310) on the upper surface of the ceramic substrate (top of 100), a dielectric layer ([0044], 350) on an upper surface of the lower electrode layer (top of 310), and an upper electrode layer ([0044], 320) on an upper surface of the dielectric layer (top of 350). Suk also teaches this improves power integrity properties ([0058]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor package of Kang to include the capacitor of Suk to improve power integrity properties.
Regarding Claim 14, Suk (fig. 1B) teaches the semiconductor package of claim 13, wherein the lower electrode layer (310) is connected to the first circuit wiring layer ([0049], 161, 163), and the upper electrode layer (320) is connected to the third circuit wiring layer (151, 153).
Regarding Claim 15, Suk (fig. 1B) teaches the semiconductor package of claim 13, wherein the lower electrode layer (310) comprises the same material ([0044], [0049], both 310 and 163 may be a metal) as the first circuit wiring layer (161, 163), and the upper electrode layer (320) comprises the same material ([0043]-[0044], both 320 and 153 may be metal) as the third circuit wiring layer (151, 153).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kang as applied to Claim 1 above, and further in view of Ong et al. (2021/0384133 A1; hereinafter Ong).
Regarding Claim 10, Kang doesn’t teach the semiconductor package of claim 1, wherein the bridge chip structure further comprises one or more of a capacitor, an inductor, and a switch.
However, Ong (fig. 1) teaches the bridge chip structure ([0027], 107) further comprises one or more of a capacitor, an inductor, and a switch ([0027]). Ong also teaches that passive bridges may serve as power delivery and an active bridge serves to route signals ([0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor package of Kang to include the capacitor, inductor, or switch of Ong to provide either power delivery or signal routing.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kang and Suk as applied to Claim 15 above, and further in view of Kim et al. (2017/0287853 A1; hereinafter Kim).
Regarding Claim 16, Kang doesn’t teach the semiconductor package of claim 15, wherein the lower electrode layer comprises silver or tungsten, and the upper electrode layer comprises at least one of copper, nickel, gold, platinum, titanium, chromium, or alloys thereof.
However, Kim (fig. 18A) teaches the lower electrode layer ([0125], 192a) comprises silver or tungsten ([0125]), and the upper electrode layer ([0125], 192b) comprises at least one of copper, nickel, gold, platinum, titanium, chromium, or alloys thereof ([0125], 192a and 192b may be different metals from each other). One of ordinary skill in the art would have found it obvious to try different metals for a capacitor and yielded the predictable results of a functional capacitor.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to use different materials in a capacitor since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Suk.
Regarding Claim 18, Kang (fig. 1) teaches a semiconductor package comprising:
a ceramic substrate ([0017], 110) having a cavity ([0018], CA),
the ceramic substrate (110) comprising a plurality of first insulating layers ([0019], 112), and
a first circuit wiring layer ([0019], 114) between the plurality of first insulating layers (112);
a lower redistribution structure ([0017], 140) on a lower surface of the ceramic substrate (bottom surface of 110),
the lower redistribution structure (140) comprising a plurality of second insulating layers ([0033], 142) and
a second circuit wiring layer ([0033], 144) between the plurality of second insulating layers (142) and electrically connected to the first circuit wiring layer (114);
an upper redistribution structure ([0019], 130) on an upper surface of the ceramic substrate (top of 110),
the upper redistribution structure (130) comprising a plurality of third insulating layers ([0033], 132) and
a third circuit wiring layer ([0033], 134) between the plurality of third insulating layers (132) and electrically connected to the first circuit wiring layer (114);
a plurality of semiconductor chips ([0016], 200, 300) arranged in a first direction (up and down, see fig. 1) on the upper redistribution structure (130) and comprising a logic semiconductor chip ([0035]) or a high bandwidth memory (HBM) semiconductor chip;
a bridge chip structure ([0017], 120) in the cavity (CA) of the ceramic substrate (110) and comprising a bridge chip (120) electrically connecting the plurality of semiconductor chips (200, 300) to each other; and
an encapsulation layer ([0031], 113) encapsulating the bridge chip structure (120) within the cavity (CA), wherein the encapsulation layer (113) comprises ceramic material, resin ([0031]), or a combination thereof; and
a capacitor structure at an interface between the ceramic substrate and the upper redistribution structure,
the capacitor structure comprising a lower electrode layer on the upper surface of the ceramic substrate,
a dielectric layer on an upper surface of the lower electrode layer, and
an upper electrode layer on an upper surface of the dielectric layer.
Kang doesn’t teach a capacitor structure at an interface between the ceramic substrate and the upper redistribution structure, the capacitor structure comprising a lower electrode layer on the upper surface of the ceramic substrate, a dielectric layer on an upper surface of the lower electrode layer, and an upper electrode layer on an upper surface of the dielectric layer.
However, Suk (fig. 1B) teaches a capacitor structure ([0044], 300) at an interface between the ceramic substrate ([0044], 100) and the upper redistribution structure ([0042], [0065], 151, 153, 410), the capacitor structure (300) comprising a lower electrode layer ([0044], 310) on the upper surface of the ceramic substrate (top of 100), a dielectric layer ([0044], 350) on an upper surface of the lower electrode layer (top of 310), and an upper electrode layer ([0044], 320) on an upper surface of the dielectric layer (top of 350). Suk also teaches this improves power integrity properties ([0058]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor package of Kang to include the capacitor of Suk to improve power integrity properties.
Regarding Claim 19, Suk (fig. 1B) teaches the semiconductor package of claim 18, wherein the lower electrode layer (310) is connected to the first circuit wiring layer ([0049], 161, 163), and the upper electrode layer (320) is connected to the third circuit wiring layer (151, 153).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kang and Suk as applied to Claim 18 above, and further in view of Qian.
Regarding Claim 20, Kang doesn’t teach the semiconductor package of claim 18, wherein a vertical depth of the cavity into the ceramic substrate is in a range of about 80 μm to about 200 μm.
However, Qian (fig. 2) teaches a depth of the cavity ([0040], cavity where 212 is formed) into the ceramic substrate ([0039]-[0041], 204, 210, 220) is in a range of about 80 μm to about 200 μm ([0068], cavity made for the bridge die ranges from 25 μm to 400 μm). Depths, however, will not support the patentability of the subject matter encompassed by the prior art unless there is evidence indicating such depths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality of the claimed depth, and similar depths are used for embedded bridge dies in the art, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select the appropriate depth for an embedded bridge die.
Conclusion
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/A.H./Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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