Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications December 31, 2025, claims 1-20 are active in
this application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Johnson et al. [US Patent # 10,504,571].
With respect to claim 19, Johnson et al. disclose a packaged memory device [fig. 1] comprising: a primary memory die [110] coupled to a shared intra-package communication bus [140] and coupled to an external host device ["The memory device 100 can include multiple semiconductor dies/chips that are electrically coupled to each other and to an external controller" - col. 3, lines 10-20] using a host interface bus [c/a]; and multiple secondary dies coupled to the intra-package communication bus [“...the master die and the slave dies 112 can communicate various signals (e.g., data (DQ)) to/from the controller through corresponding input/output (I/O) busses.” —col. 3, lines 25-30] and decoupled from the host interface bus [this depends on the master die] , wherein each of the secondary dies is configured to receive the same messages from the primary memory die using the intra-package communication bus [“...the master die 110 can broadcast the calibration enable 136 and the calibration clock 134 to all of the slave dies 112.” —col. 3, lines 40-50]; and wherein each of the secondary dies has a respective die-specific identifier ["...channel slave decoder 510 (e.g., at the slave dies 112) can include logic configured to indicate if a corresponding die should access the ZQ resistor according to the die identifier." – col. 10, lines 24-40] and each of the secondary dies comprises respective logic circuitry configured to compare information ["The channel slave decoder 510 can generate a die match signal (DieMatch) 608 when the die identifier matches the identification information of the corresponding die." – col. 10, lines 24-40] from a die identification field in each of the messages ["...channel slave decoder 510 for the 1st slave die can generate the die match signal 608 when the die identifier matches the identifier for the 1st slave die." (Implicitly, the "die identifier" mentioned is part of a received message/command). - – col. 10, lines 24-40] to the die-specific identifier and determine whether to respond to each of the messages ["The die match signal 608 can be used (e.g., at the channel start block 501) to generate the local start signal 610 for the corresponding die." (The "local start signal" is the response to the message).- col. 10, lines 24-40] from the primary memory die [Implicit in the context of a "channel start block 501" controlling "slave dies 112" (a typical primary-secondary/controller-die architecture). – col. 10, lines 24-40].
With respect to claim 20, Johnson et al. disclose the primary memory die comprises logic circuitry configured to determine whether to respond to a message from one of the secondary dies, wherein the message from one of the secondary dies comprises a die identification field with a die identifier that uniquely identifies the primary memory die [“The master die 110 can coordinate one or more process between the dies and/or provide interactions or interface functions between the slave dies 112 and systems/devices external to the memory device 100. For example, the master die 110 can receive commands (e.g., aZQ calibration command), data, address from the controller through a command/address bus (C/A). Also, the master die and the slave dies 112 can communicate various signals (e.g., data (DQ)) to/from the controller through corresponding input/output (I/O) busses.” —col. 3, lines 20-35].
Remarks
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Allowable Subject Matter
Claims 1-18 are allowable over the prior art of records.
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 1, the second die corresponds to a first chip identifier; and a third die coupled to the shared bus. wherein the third die corresponds to a second chip identifier; wherein the first die is configured to use a selected one of the first chip identifier and the second chip identifier to communicate, via the shared bus, with the corresponding one of the second die and the third die, and wherein when the first die communicates a first message with the first chip identifier using the shared bus, the third die is configured to disregard information on the shared bus.
-with respect to claim 14, the third die is uniquely identified by a second identifier: wherein the first die is configured to communicate, via the shared bus, a first message to the second die and the third die, and wherein when the first message comprises an identification field with the first identifier, the second die is configured to receive read and/or write messages from the first die.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 February 11, 2026