Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments and Arguments
Amendments and arguments filed on 01/09/2026 have been fully considered and are not found to place the application in a condition for allowance. While Qing does not teach that the second power voltage is different from the previous stage gate signal, Kim teaches a transistor (fig. 3, M1) similar to T7 of Qing which receives a second power voltage as claimed. Kim teaches in ¶ 88 that based on such a configuration “the manufacturing cost is substantially reduced and the reliability of driving is substantially improved.” Accordingly, the limitations are found to be taught based on the teachings of Qing in view of Kim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5-7, 11, 14 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Qing et al., US 2015/0228353 A1, hereinafter “Qing”, in view of Kim et al., US 2014/0375616 A1, hereinafter “Kim”.
Regarding claim 1, Qing teaches a gate driver (¶ 62, shift register) comprising a plurality of stages (¶ 62), at least one stage of the plurality of stages comprising: a first transistor (fig. 5, T8) including a control electrode configured to receive a first clock signal (CKB), a first electrode configured to receive a previous stage gate signal (OUT(n-1), ¶ 62), and a second electrode connected to a first node (fig. 5, see the connection node between T8 and T7); a third transistor (T2) including a control electrode directly connected to the control electrode of the first transistor and configured to directly receive the first clock signal (fig. 5, see gate connections of T2 and T8), a first electrode configured to receive a first power voltage (VGL1), and a second electrode connected to a third node (OUT(n)); a fourth transistor (T1) including a control electrode connected to a second node (PU), a first electrode configured to receive a second clock signal different from the first clock signal (CK, per fig. 7, CK and CKB are different), and a second electrode connected to the third node (see fig. 5); and a first capacitor (C) including a first electrode connected to the second node and a second electrode connected to the third node (see fig. 5), wherein the least one stage is configured to output a voltage of the third node as a gate signal (¶ 63); and a second transistor (fig. 5, T7) including a control electrode configured to receive a second power voltage different from the first power voltage (¶ 28, OUT(n-1) is a driving signal input terminal which per fig. 7 provides VGH), a first electrode connected to the first node, and a second electrode connected to the second node (see fig. 5).
Qing does not teach a second power voltage different from the previous stage gate signal.
Kim, however, teaches a second transistor (fig. 3, M1) including a control electrode configured to receive a second power voltage (VSS) different from the first power voltage (VDD), and a previous stage gate signal (VDD is different from SSP or the previous stage gate signal as seen in fig. 3 for ST2).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Qing and Kim. The references teach gate driving circuits and Kim further teaches the use of a transistor M1 which is configured to receive a second power voltage as claimed. Furthermore, note that in ¶ 55 Kim teaches that the transistors may be n-type transistors similar to those of Qing. One would have been motivated to make such a combination in order to improve the reliability and reduce manufacturing costs of the driving circuit as taught by Kim in ¶ 88.
Regarding claim 5, Qing teaches that the fourth transistor is configured to be turned on based on the previous stage gate signal having an activation level in a first period (fig. 7, see the “pre-charging phase”, ¶ 54).
Regarding claim 6, Qing teaches that in a second period subsequent to the first period, the first clock signal has an inactivation level (fig. 7, see period 2 during which CKB is low), the second clock signal has an activation level (fig. 7, CK is high during period 2).
Qing does not specifically teach that during the second period a voltage of the second node is lower than a low voltage of the second clock signal.
Kim teaches that during the second period a voltage of the second node is lower than a low voltage of the second clock signal (fig. 5, see the voltage of N2 at -20v compared to CLK2 at -8v during the second period).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Qing in view of Kim to achieve such a configuration. The references teach shift registers for outputting scan signals and Kim further teaches that such a circuit may be configured with n-type or p-type transistors (Kim ¶ 55) according to which the polarity and types of voltages applied to the transistors are inversed and during the second period a voltage of the second node is lower than a low voltage of the second clock signal. One would have been motivated to make such a modification with the expectation of achieving the same results of providing scan driving signals as taught by the references.
Regarding claim 11, Qing teaches a gate driver (¶ 62, shift register) comprising a plurality of stages (¶ 62), at least one stage of the plurality of stages comprising: a first transistor (fig. 5, T8) configured to apply a previous stage gate signal (OUT(n-1), ¶ 62) to a first node (fig. 5, see the connection node between T8 and T7) in response to a first clock signal (CKB); a second transistor (T7) connected between the first node and a second node (T7 is connected between the first node and PU); a third transistor (T2) having a control electrode directly connected to a control electrode of the first transistor (fig. 5, see gate connections of T2 and T8) and configured to directly receive the first clock signal (see fig. 5) and the third transistor being configured to apply a first power voltage (VGL1) to a third node (OUT(n)); a fourth transistor (T1) configured to apply a second clock signal (CK) different from the first clock signal (per fig. 7, CK and CKB are different) to the third node in response to a voltage of the second node (see fig. 5 and fig. 7); and a first capacitor (C) connected between the second node and the third node (see fig. 5), wherein the least one stage is configured to output a voltage of the third node as a gate signal (¶ 63); and the second transistor includes a control electrode configured to receive a second power voltage different from the first power voltage (¶ 28, OUT(n-1) is a driving signal input terminal which per fig. 7 provides VGH).
Qing does not teach a second power voltage different from the previous stage gate signal.
Kim, however, teaches a second transistor (fig. 3, M1) including a control electrode configured to receive a second power voltage (VSS) different from the first power voltage (VDD), and a previous stage gate signal (VDD is different from SSP or the previous stage gate signal as seen in fig. 3 for ST2).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Qing and Kim. The references teach gate driving circuits and Kim further teaches the use of a transistor M1 which is configured to receive a second power voltage as claimed. Furthermore, note that in ¶ 55 Kim teaches that the transistors may be n-type transistors similar to those of Qing. One would have been motivated to make such a combination in order to improve the reliability and reduce manufacturing costs of the driving circuit as taught by Kim in ¶ 88.
Regarding claim 14, Qing teaches a display device (¶ 63) comprising: a display panel (¶ 63; the disclosed display devices necessarily include a display panel); a gate driver (¶ 63) configured to output a gate signal to a gate line of the display panel (¶ 63, “provide line-by-line scan function”); and a data driver configured to output a data voltage to a data line of the display panel (such a data driver and data line is inherent to the disclosed display devices), wherein the gate driver comprises a plurality of stages (¶ 63), wherein at least one stage of the plurality of stages comprises: a first transistor (fig. 5, T8) including a control electrode configured to receive a first clock signal (CKB), a first electrode configured to receive a previous stage gate signal (OUT(n-1), ¶ 62), and a second electrode connected to a first node (fig. 5, see the connection node between T8 and T7); a second transistor (fig. 5, T7) including a control electrode configured to receive a second power voltage different from the first power voltage (¶ 28, OUT(n-1) is a driving signal input terminal which per fig. 7 provides VGH), a first electrode connected to the first node, and a second electrode connected to a second node (see connection to PU); a third transistor (T2) including a control electrode directly connected to the control electrode of the first transistor and configured to directly receive the first clock signal (fig. 5, see gate connections of T2 and T8), a first electrode configured to receive a first power voltage (VGL1), and a second electrode connected to a third node (OUT(n)); a fourth transistor (T1) including a control electrode connected to the second node (PU), a first electrode configured to receive a second clock signal different from the first clock signal (CK, per fig. 7, CK and CKB are different), and a second electrode connected to the third node (see fig. 5); and a first capacitor (C) including a first electrode connected to the second node and a second electrode connected to the third node (see fig. 5), wherein the least one stage is configured to output a voltage of the third node as a gate signal (¶ 63).
Qing does not teach a second power voltage different from the start signal.
Kim, however, teaches a second transistor (fig. 3, M1) including a control electrode configured to receive a second power voltage (VSS) different from the start signal (fig. 3, VDD is different from SSP).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Qing and Kim. The references teach gate driving circuits and Kim further teaches the use of a transistor M1 which is configured to receive a second power voltage as claimed. Furthermore, note that in ¶ 55 Kim teaches that the transistors may be n-type transistors similar to those of Qing. One would have been motivated to make such a combination in order to improve the reliability and reduce manufacturing costs of the driving circuit as taught by Kim in ¶ 88.
Regarding claim 17, Qing teaches that the fourth transistor is turned on based on the start signal having an activation level in a first period (fig. 7, see the “pre-charging phase”, ¶ 54; Also see STV in ¶ 24).
Regarding claim 18, Qing teaches that in a second period subsequent to the first period, the first clock signal has an inactivation level (fig. 7, see period 2 during which CKB is low), the second clock signal has activation level (fig. 7, CK is high during period 2).
Qing does not specifically teach that during the second period a voltage of the second node is lower than the second power voltage.
Kim teaches that during the second period a voltage of the second node is lower than the second power voltage (fig. 5, ¶ 81 and ¶ 89).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Qing in view of Kim to achieve such a configuration. The references teach shift registers for outputting scan signals and Kim further teaches that such a circuit may be configured with n-type or p-type transistors (Kim ¶ 55) according to which the polarity and types of voltages applied to the transistors are inversed and during the second period a voltage of the second node is lower than a low voltage of the second clock signal. One would have been motivated to make such a modification with the expectation of achieving the same results of providing scan driving signals as taught by the references.
Regarding claims 7 and 19, Qing teaches that in a third period subsequent to the second period (fig. 7, period 3), the first clock signal has an activation level, the second clock signal has an inactivation level and the gate signal has an inactivation level (fig. 7, see period 3 during which CKB is high (activation level), CK is low (inactivation level) and OUT(n) is low).
Claims 3-4, 8, 12-13, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Qing and Kim, as applied above, further in view of Xiao et al., US 2025/0081610 A1, hereinafter “Xiao”.
Regarding claims 3, 12 and 15, Qing and Kim do not specifically teach that a ratio of a channel width to a channel length of the third transistor is different from a ratio of a channel width to a channel length of the fourth transistor.
Xiao, however, teaches that a ratio of a channel width to a channel length of the third transistor is different from a ratio of a channel width to a channel length of the fourth transistor (fig. 6, teaches a gate driver similar to the instant application. T24 is analogous to the third transistor and T25 is analogous to the fourth transistor. Fig. 18 further teaches that T24 and T25 have different W/L ratios wherein AT24 and AT25 are the channel regions of T24 and T25, respectively).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Qing, Kim and Xiao. The references teach similar gate driving circuits and Xiao further teaches details regarding the manufacturing of such gate driving circuits. As such, one would have been motivated to make such a combination in order to appropriately manufacture the circuit as taught by Qing by incorporating the layout details as provided in Xiao.
Regarding claims 4, 13 and 16, Qing and Kim do not teach that a channel width of the third transistor is narrower than a channel width of the fourth transistor.
Xiao, however, teaches that a channel width of the third transistor (fig. 6, T24; also see fig. 18: the channel width AT24 extending vertically) is narrower than a channel width of the fourth transistor (fig. 6, T25; also see fig. 18: the channel width AT25 extending vertically).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Qing, Kim and Xiao. The references teach similar gate driving circuits and Xiao further teaches details regarding the manufacturing of such gate driving circuits. As such, one would have been motivated to make such a combination in order to appropriately manufacture the circuit as taught by Qing by incorporating the layout details as provided in Xiao.
Regarding claim 8, Qing teaches that the at least one stage further comprises a second transistor (fig. 5, T7) including a control electrode configured to receive a second power voltage different from the first power voltage (¶ 28, OUT(n-1) is a driving signal input terminal which per fig. 7 provides VGH), a first electrode connected to the first node, and a second electrode connected to the second node (see fig. 5).
Qing and Kim do not teach that a channel length of the first transistor is longer than a channel length of the second transistor.
Xiao, however, teaches that a channel length of the first transistor (fig. 6, T21) is longer than a channel length of the second transistor (fig. 6, T28; see fig. 18 wherein a channel length of AT21 is longer than a channel length of AT28).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Qing, Kim and Xiao. The references teach similar gate driving circuits and Xiao further teaches details regarding the manufacturing of such gate driving circuits. As such, one would have been motivated to make such a combination in order to appropriately manufacture the circuit as taught by Qing by incorporating the layout details as provided in Xiao.
Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Qing and Kim, as applied above, further in view of Minami et al., US 2012/0013590 A1, hereinafter “Minami”.
Regarding claims 9 and 20, Qing teaches that a phase of the second clock signal is opposite to a phase of the first clock signal (see fig. 7, CK and CKB).
Qing and Kim do not specifically teach that an activation level period of the first clock signal is longer than an inactivation level period of the first clock signal.
Minami, however, teaches that an activation level period of the first clock signal is longer than an inactivation level period of the first clock signal (fig. 9, ¶ 132).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Qing, Kim and Minami. The references teach the use of oppositely phased clock signals to drive scan signals for a display device. Minami, further teaches an alternative configuration of providing such clock signals, wherein the active period is longer than the inactive period. As such, one would have been motivated to modify Qing in view of Minami expecting the same results of properly outputting a scan signal.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Qing and Kim, as applied above, further in view of Wu et al., US 2019/0164499 A1, hereinafter “Wu”.
Regarding claim 10, Qing and Kim do not specifically teach that the least one stage further comprises a first-second transistor connected in series with the first transistor, and wherein the first-second transistor includes a control electrode configured to receive the first clock signal, a first electrode connected to a fourth node and a second electrode connected to the first node.
Wu teaches that the least one stage further comprises a first-second transistor connected in series with the first transistor (fig. 3, see the two series transistors of M1), and wherein the first-second transistor includes a control electrode configured to receive the first clock signal, a first electrode connected to a fourth node and a second electrode connected to the first node (see fig. 3).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Qing, Kim and Wu. The references teach similar gate driving circuits and Wu further teaches that a transistor such as the first transistor may be configured as a “double-gate” transistor which meets the configuration as claimed. One would have been motivated to make such a combination since Wu clearly teaches that such a configuration reduces “parasitic parameters” and increases “a cut-off frequency” (see ¶ 34).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEPEHR AZARI whose telephone number is (571)270-7903. The examiner can normally be reached weekdays from 11AM-7PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at (571) 272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEPEHR AZARI/ Primary Examiner, Art Unit 2621