DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 06/12/2024 and 03/17/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
“SEMICONDUCTOR DEVICES INCLUDING GROUPS OF DUMMY CHANNELS AND DATA STORAGE SYSTEMS INCLUDING THE SAME”
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract is objected to because it contains more than 150 words (~242 words). Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 12-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin (U.S. PG Pub No US2019/0027490A1).
Regarding claim 1, Shin teaches a semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] (refer to fig. 11 for top/plan view information) comprising:
a stack structure (120 with 130) fig. 4B [0032-0035] (refer to figs. 4A-4D for cross-sectional information) [0031-0032] including gate electrodes (130) fig. 4B [0035] that are spaced apart from each other in a first (z) direction, perpendicular to an upper surface of a substrate (101) fig. 4B [0032], in a first region (I) and a second region (II);
separation regions (MS1, MS2) fig. 11 [0049] (‘isolation’/separation regions) extending (vertically) through the stack structure [see fig. 4D, 0049] and extending in a second (x) direction, perpendicular to the first (z) direction, in the first region (I) and the second region (II);
a plurality of channel structures (CH) fig. 11 [0040-0042] extending through the stack structure (see fig. 4B), in a cell region (CE) (CH defining memory cells [0033-0035]) of the first region (I) (see annotated fig. 11 below);
a plurality of dummy channel structures (DCH1-3) fig. 11 [0045-0046] extending through the stack structure (120, 130), in a buffer region (BU) (at a buffer space between I and II) of the first region (I) (see annotated fig. 11 below); and
a plurality of support structures (SS) fig. 11 [0051, 0054] (acting to provide isolation/inert material support to upper portion of stack [0051, 0054]) extending (at least partially) through the stack structure (120, 130) (see fig. 4D), (at least partially) in the second region (II) (see fig. 11),
wherein the first region (I) and the second region (II) are sequentially arranged in the second (x) direction,
wherein the separation regions (MS1-2) include a first separation region (upper MS1) (upper in fig. 11 perspective) and a second separation region (lower MS1) (lower in fig. 11 perspective), adjacent (nearby) to each other in a third (z) direction, and perpendicular to the first (y) direction and the second (x) direction,
wherein, between the first (upper MS1) and second (lower MS1) separation regions, the dummy channel structures (DCH1-3) include a first dummy group (DG1) (see annotated fig. 11 below) adjacent (nearby) to the cell region (CE) and including first dummy channel structures (DCH in DG1) sequentially arranged in the third (z) direction, and a second dummy group (DG2) (see annotated fig. 11 below) adjacent (nearby) to the second region (II) and including second dummy channel structures (DCH in DG2) sequentially arranged in the third (z) direction, and
wherein a first length (L1) (end-to-end length of entire group) of the first dummy group (DG1) in the third (z) direction is longer than a second length (L2) (end-to-end length of entire group) of the second dummy group (DG2) in the third (z) direction (L1>L2; as defined in annotated fig. 11 of Shin below).
[AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (L2)][AltContent: textbox (L3)][AltContent: textbox (L1)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (DG2)][AltContent: textbox (DG3)][AltContent: textbox (DG1)][AltContent: oval][AltContent: oval][AltContent: connector][AltContent: connector][AltContent: oval][AltContent: connector][AltContent: textbox (CO)][AltContent: textbox (BO)][AltContent: textbox (BU)][AltContent: textbox (CE)][AltContent: rect][AltContent: rect][AltContent: rect][AltContent: rect]
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Annotated fig. 11 of Shin
Regarding claim 2, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 1. Shin also teaches wherein a distance between the first separation region (upper MS1) fig. 11 [0049] and the (midpoint of the) second dummy group (DG2) is substantially identical to a distance between the second separation region (lower MS1) fig. 11 [0049] and the (midpoint of the) second dummy group (DG2) (DG2 defined symmetrically between upper and lower MS1; see annotated fig. 11 above).
Regarding claim 3, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 1. Shin also teaches wherein between the first (upper MS1) fig. 11 [0049] and second (lower MS1) separation regions, the dummy channel structures (DCH1-3) fig. 11 [0045-0046] sequentially further include a third dummy group (DG3) including third dummy channel structures (DCH in DG3) sequentially arranged in the third (z) direction (horizontally) between the first dummy group (DG1) and the second dummy group (DG2), and
wherein a third length (L3) (end-to-end length of entire group) of the third dummy group (DG3) in the third (z) direction is shorter than the first length (L1) of the first dummy group (DG1) in the third (z) direction and is longer than the second length (L2) of the second dummy group (DG2) in the third (z) direction (L1>L3>L2; as defined in annotated fig. 11 above).
Regarding claim 4, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 3. Shin also teaches wherein a number (8) of the first dummy channel structures (DCH) [0045-0046] in the first dummy group (DG1), a number (3) of the second dummy channel structures (DCH) in the second dummy group (DG2), and a number (4) of the third dummy channel structures (DCH) in the third dummy group (DG3) are different from each other (groups defined as having distinct total numbers of DCH’s, as defined in annotated fig. 11 above)
Regarding claim 5, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 3. Shin also teaches wherein a ratio of a distance (0) between the first separation region (upper MS1) fig. 11 [0049] and the second dummy group (DG2) in the second (x) direction and a distance (0) between the first separation region (upper MS1) and the third dummy group (DG3) in the second (x) direction is substantially identical to a ratio of a distance (0) between the first separation region (upper MS1) and the third dummy group (DG3) in the second (x) direction and a distance (0) between the first separation region (upper MS1) and the second dummy group (DG2) in the second (x) direction (DG2 and DG3 are coplanar with upper MS1 in x direction, such that there is no (0) horizontal spacing between each of DG2, DG3 and a coplanar point of upper MS1; ratio of 0:0 defined in both cases).
Regarding claim 6, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 3. Shin also teaches wherein a ratio of a distance (greater distance) between the first separation region (upper MS1) fig. 11 [0049] and the second dummy group (DG2) in the second (x) direction and a distance (lesser distance) between the first separation region (upper MS1) and the third dummy group (DG3) in the second (x) direction (defined as a horizontal distance between upper MS1 starting at level of interface of regions I and II, to respective dummy group DG3/DG2) is different from a ratio of a distance (lesser distance) between the first separation region (upper MS1) and the third dummy group (DG3) in the second (x) direction and a distance (greater distance) between the first separation region (upper MS1) and the second dummy group (DG2) in the second (x) direction (distances are defined as horizontal distances between upper MS1 starting at level of interface of regions I and II, to respective dummy group DG3/DG2 – DG3 is closer to this point than DG2, thus a lesser distance exists between them; ratio of lesser distance : greater distance “different from” ratio of greater distance : lesser distance).
Regarding claim 7, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 1. Shin also teaches wherein a first interval (vertical separation) between respective (nearest neighbors) ones of the first dummy channel structures (DCH in DG1) fig. 11 [0045-0046] in the third (z) direction is greater than a second interval (vertical separation) between respective ones of the second dummy channel structures (DCH in DG2) fig. 11 [0045-0046] in the third (z) direction (neighboring DCH in DG1 are clearly separated by a greater interval in z direction than DCH in DG2, as defined in annotated fig. 11 above).
Regarding claim 12, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 1. Shin also teaches wherein the channel structures (CH) fig. 11 [0040-0042] and the dummy channel structures (DCH1-3) fig. 11 [0045-0046] include a first material (140 channel layer formed of silicon semiconductor [0041, 0045]) (same 140 layer structure [0045]), and the support structures (SS) fig. 11 [0051, 0054] (comprising insulating material 103 [0051]) do not include the first material (SS formed of insulating material [0051], not semiconductor silicon material [0041, 0045]).
Regarding claim 13, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 1. Shin also teaches wherein each of the channel structures (CH) fig. 11 [0040-0042] has a first width (taken at bottommost level of CH in fig. 4B in x direction),
at least one of the dummy channel structures (DCH1-3) fig. 11 [0045-0046] has a second width (taken at topmost level of DCH1 in fig. 4D in x direction) greater than the first width (DCH1-3) fig. 11 [0045-0046] (CH/DCH appear slightly tapered such that top is slightly wider in x direction than bottom [0045]), and at least one of the support structures (SS) fig. 11 [0051, 0054] has a third width (in x direction) greater than the second width (SS clearly wider in x direction than top of DCH in fig. 11).
Regarding claim 14, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 1. Shin also teaches wherein the channel structures (CH) fig. 11 [0040-0042] are disposed symmetrically about (centered about) an axis with one of the separation regions (middle MS2) fig. 11 [0049] extending in the second (x) direction as the (central) axis.
Regarding claim 15, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 1. Shin also teaches wherein between the first separation region (upper MS1) and the second separation region (lower MS1), an arrangement (shape of collective arrangement of objects) of the channel structures (CH) fig. 11 [0040-0042] is different from an arrangement (shape of collective arrangement of objects) of the dummy channel structures (DCH1-3) fig. 11 [0045-0046] (different lattice array-arrangement).
Regarding claim 16, Shin teaches a semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] (refer to fig. 11 for top/plan view information) comprising:
a stack structure (120 with 130) fig. 4B [0032-0035] (refer to figs. 4A-4D for cross-sectional information) [0031-0032] in (at least partially in) a first region (I) [0032] and a second region (II) [0032] and including gate electrodes (130) fig. 4B [0035] and interlayer insulating layers (120) fig. 4B [0032] alternately stacked;
a plurality of separation regions (MS1’s) fig. 11 [0049] (‘isolation’/separation regions) extending through the stack structure (120, 130) in a third (z) direction;
a plurality of channel structures (CH) fig. 11 [0040-0042] extending through the stack structure, in a cell region (CE) (CH defining memory cells [0033-0035]) of the first region (I) (see annotated fig. 11 below);
a plurality of dummy vertical structures (DCH1-3) fig. 11 [0045-0046] extending (vertically) through the stack structure (120, 130), in a buffer region (BU) (at a buffer space between I and II) of the first region (I) (see annotated fig. 11 below);
a plurality of first support structures (SS) fig. 11 [0051, 0054] (acting to provide isolation/inert material support to upper portion of stack [0051, 0054]) extending (at least partially) through the stack structure (120, 130) (see fig. 4D), in a boundary region (BR) (at a boundary region between I and II) of the second region (II) (see annotated fig. 11 below);
contact plugs (MC) fig. 11 [0037, 0066] (see fig. 11 for CP in region II) connected to contact regions (areas of increased thickness CP) [0037, 0066] of the gate electrodes, in a connection region (CO) of the second region (see annotated fig. 11 below); and
a plurality of second support structures (MS2) fig. 11 [0060, 0032, 0045] (providing support through inert/isolation material) extending through the stack structure (120, 130) (see fig. 4B), in (at least partially) the connection region (CO) of the second region (II) (see fig. 11),
wherein the cell region (CE) of the first region (I), the buffer region (BR) of the first region (I), the boundary region (BO) of the second region (II), and the connection region (CO) of the second region are sequentially disposed in a second (x) direction (as defined in annotated fig. 11 below),
wherein the separation regions (MS1’s) include a first separation region (upper MS1) (upper in fig. 11 perspective) and a second separation region (lower MS1) (lower in fig. 11 perspective), adjacent (nearby) to each other in a third (z) direction, and perpendicular to the first (y) direction and the second (x) direction, and
wherein between a first central axis of the first separation region (upper MS1) extending in the second (x) direction and a second central axis of the second separation region (lower MS1) extending in the second (x) direction, distances between first dummy vertical structures (distances between pairs of dummy vertical structures DVS1-2) (as defined in annotated fig. 11 below) adjacent to the first separation region (upper MS1) among the dummy vertical structures (DCH1-3) and the first central axis increase from a region (DVS1) adjacent to (nearby) the cell region (CE) of the first region (I) to a region (DVS2) adjacent to (nearby) the boundary region (BR) of the second region (II) (DVS2 pair separated by greater distance line than DVS1 pair separation distance line - as defined in annotated fig. 11 of Shin below).
[AltContent: textbox (DVS2 )][AltContent: textbox (DVS1 )][AltContent: arrow][AltContent: arrow][AltContent: connector][AltContent: connector][AltContent: textbox (CO)][AltContent: textbox (BO)][AltContent: textbox (BU)][AltContent: textbox (CE)][AltContent: rect][AltContent: rect][AltContent: rect][AltContent: rect]
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Annotated fig. 11 of Shin
Regarding claim 17, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 16. Shin also teaches wherein the channel structures (CH) fig. 11 [0040-0042] include a channel layer (140 of CH) fig. 4B [0032],
wherein the dummy vertical structures (DCH1-3) fig. 11 [0045-0046] include a dummy channel layer (140 of DCH1-3) fig. 4D [0032, 0041, 0045],
wherein the channel layer (140 of CH) and the dummy channel layer (140 of DCH1-3) include a first material (silicon semiconductor [0041, 0045]) (same 140 layer structure [0045]), and
wherein the first (SS) fig. 11 [0051, 0054] (comprising SS material 103 [0051]) support structures and the second (MS2) fig. 11 [0060, 0032, 0045] (comprising 107 [0050]) support structures include a support insulating layer (103 and 107, respectively [0050-0051]) (insulating layer(s) acting to provide inert support to stack), and (insulating layers) do not include the first material (silicon semiconductor).
Regarding claim 18, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 16. Shin also teaches wherein a width (taken at bottommost level of CH in fig. 4B in x direction) of the channel structures (CH) fig. 11 [0040-0042] is less than a width (taken at topmost level of DCH1 in fig. 4D in x direction) of the dummy vertical structures (DCH1-3) fig. 11 [0045-0046] (CH/DCH appear slightly tapered such that top is slightly wider in x direction than bottom [0045]), and the width (shown as width of top of DCH1 in x direction of fig. 11) of the dummy vertical structures (DCH1-3) fig. 11 [0045-0046] is less (clearly) than a width (in x direction) of the first (SS) fig. 11 [0051, 0054] and second (MS2) fig. 11 [0060, 0032, 0045] support structures (see fig. 11).
Regarding claim 19, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 16. Shin also teaches wherein between the first central axis of the first separation region (upper MS1) extending in the second (x) direction and the second central axis of the second separation region (lower MS1) extending in the second (x) direction, an arrangement (shape of collective arrangement of objects) of the plurality of dummy vertical structures (DCH1-3) fig. 11 [0045-0046] is different from an arrangement (shape of collective arrangement of objects) of the plurality of channel structures (CH) fig. 11 [0040-0042] and an arrangement (shape of collective arrangement of objects) of the plurality of first support structures (SS) fig. 11 [0051, 0054].
Regarding claim 20, Shin teaches a data storage system (10) fig. 1 [0020] (for storing memory date) comprising:
a semiconductor storage device (20 with 32 and 34) fig. 1 [0020-0022] including a first semiconductor structure (34) including circuit elements (column decoder and sense amplifier) [0024], a second semiconductor structure (20 comprising 100) fig. 1 [0021, 0031] on (supported by) one surface of the first semiconductor structure (34), and an input/output pad (surface of BL for connections) fig. 1[0021, 0024] (exchange input/output signals with) [0024-0025] electrically connected to the circuit elements (34) [0024];
a controller (36) electrically connected [0025] to the semiconductor storage device (20 with 32 with 34) (partially) through the input/output pad (BL’s) [0024-0025, 0029] and configured to control [0025] the semiconductor storage device (20 with 32 with 34),
wherein the second semiconductor structure (20 comprising 100F/100) fig. 11 [0032, 0059, 0066, 0068] (refer to fig. 11 for top/plan view information) comprises:
a stack structure (120 with 130) fig. 4B [0032-0035] (refer to figs. 4A-4D for cross-sectional information) [0031-0032] in (at least partially in) a first region (I) [0032] and a second region (II) [0032] and including gate electrodes (130) fig. 4B [0035] and interlayer insulating layers (120) fig. 4B [0032] alternately stacked;
a plurality of separation regions (MS1’s) fig. 11 [0049] (‘isolation’/separation regions) extending through the stack structure (120, 130) in a third (z) direction;
a plurality of channel structures (CH) fig. 11 [0040-0042] extending through the stack structure, in a cell region (CE) (CH defining memory cells [0033-0035]) of the first region (I) (see annotated fig. 11 below);
a plurality of dummy vertical structures (DCH1-3) fig. 11 [0045-0046] extending (vertically) through the stack structure (120, 130), in a buffer region (BR) (at a buffer space between I and II) of the first region (I) (see annotated fig. 11 below);
a plurality of first support structures (SS) fig. 11 [0051, 0054] (acting to provide isolation/inert material support to upper portion of stack [0051, 0054]) extending (at least partially) through the stack structure (120, 130) (see fig. 4D), in a boundary region (BO) (at a boundary region between I and II) of the second region (II) (see annotated fig. 11 below);
contact plugs (MC) fig. 11 [0037, 0066] (see fig. 11 for CP in region II) connected to contact regions (areas of increased thickness CP) [0037, 0066] of the gate electrodes, in a connection region (CO) of the second region (see annotated fig. 11 below); and
a plurality of second support structures (MS2) fig. 11 [0060, 0032, 0045] (providing support through inert/isolation material) extending through the stack structure (120, 130) (see fig. 4B), in (at least partially) the connection region (CO) of the second region (II) (see fig. 11),
wherein the cell region (CE) of the first region (I), the buffer region (BR) of the first region (I), the boundary region (BO) of the second region (II), and the connection region (CO) of the second region are sequentially disposed in a second (x) direction (as defined in annotated fig. 11 below),
wherein the separation regions (MS1’s) include a first separation region (upper MS1) (upper in fig. 11 perspective) and a second separation region (lower MS1) (lower in fig. 11 perspective), adjacent (nearby) to each other in a third (z) direction, and perpendicular to the first (y) direction and the second (x) direction, and
wherein between a first central axis of the first separation region (upper MS1) extending in the second (x) direction and a second central axis of the second separation region (lower MS1) extending in the second (x) direction, distances between first dummy vertical structures (distances between pairs of dummy vertical structures DVS1-2) (as defined in annotated fig. 11 below) adjacent to the first separation region (upper MS1) among the dummy vertical structures (DCH1-3) and the first central axis increase from a region (DVS1) adjacent to (nearby) the cell region (CE) of the first region (I) to a region (DVS2) adjacent to (nearby) the boundary region (BR) of the second region (II) (DVS2 pair separated by greater distance line than DVS1 pair separation distance line - as defined in annotated fig. 11 of Shin below).
[AltContent: textbox (DVS2 )][AltContent: textbox (DVS1 )][AltContent: arrow][AltContent: arrow][AltContent: connector][AltContent: connector][AltContent: textbox (CO)][AltContent: textbox (BO)][AltContent: textbox (BU)][AltContent: textbox (CE)][AltContent: rect][AltContent: rect][AltContent: rect][AltContent: rect]
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Annotated fig. 11 of Shin
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Shin (U.S. PG Pub No US2019/0027490A1), as applied in claim 1 above, in view of King (U.S. PG Pub No US2022/0068955A1).
Regarding claim 8, Shin teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 1. However, Shin does not explicitly disclose wherein at least one of the first (upper MS1) fig. 11 [0049] and second (lower MS1) fig. 11 [0049] separation regions has a first width in the cell region (CE) of the first region (I), and has a second width greater than the first width in a boundary region (BO) between the first region (I) and the second region (II) (different/variable widths not explicitly disclosed).
King teaches a semiconductor device (300) fig. 3 [0085] wherein at least one of the first (left 146) fig. 3 [0085] and second (right 146) fig. 11 [0085] separation regions (146) has a first width (W1) in the cell region of the first region (see annotated fig. 3 below), and has a second width (W2) greater than the first width (W1) in a boundary region between the first region and the second region (as defined in annotated fig. 3 of King below).
[AltContent: textbox (Cell Region of I )][AltContent: textbox (Buffer Region of I )][AltContent: connector][AltContent: textbox (W2)][AltContent: textbox (W1)][AltContent: connector][AltContent: arrow][AltContent: connector][AltContent: textbox (Boundary Region of II )][AltContent: arrow][AltContent: textbox (Decreased width(s) )][AltContent: arrow][AltContent: arrow][AltContent: textbox (Increased width )][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: arrow][AltContent: connector]
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Annotated fig. 3 of King
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Shin such that the separation regions are formed with a variable width throughout due to a wave-form trench shape [0085-0086] in order to enhance the amount of channel material [0086] as well as the relative number of the plurality of adjacent structures [0075-0077, 0086] so as to enhance the integration density [0003-0004, 0086] of the memory device components incorporated in a given area, as taught by King.
Regarding claim 9, Shin in view of King teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 8. Shin in view of King (with reference to King) also teaches at least one of the first (left 146) fig. 3 [0085] and second (right 146) fig. 3 [0085] separation regions has (partially comprises) an extension portion (entirety of 146 which extends diagonally) whose width increases and then decreases (from midsection to periphery) in a direction away from the cell region (CE) of the first region (I), and a portion of the extension portion has (comprises a portion of equal width) the second width (W2) in the boundary region (BO) between the first region (I) and the second region (II) (stepwise structure of 146 [0085-0086] periodically increases from lesser vertically width at periphery towards center, and decreases from center to periphery along outline of 146).
Regarding claim 10, Shin in view of King teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 8. Shin also teaches wherein in the third (z) direction, a minimum (horizontal) distance between (right sidewall of) the first separation region (upper MS1) fig. 11 [0049] and the second dummy channel structures (DCH in DG2) fig. 11 [0045-0046] of the second dummy group (DG2) is shorter than a minimum distance between a (right sidewall) side surface of the first separation region (upper MS1) and the plurality of channel structures (CH) fig. 11 [0040-0042] (because DG2 disposed further to right than CH’s).
Regarding claim 11, Shin in view of King teaches the semiconductor device (100F/100) fig. 11 [0032, 0059, 0066, 0068] of claim 9. Shin in view of King (with reference to King) also teaches wherein in the buffer region (see annotated fig. 3 above), a width of the extension portion increases (and decreases) stepwise (along slanted steps/sidewalls back/forth along diagonal, with step-transitions from portions of increasing and decreasing width) a (vertical) distance from the cell region increases in the second (y) direction (as defined in annotated fig. 3 of King above).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature three-dimensional memory device with arrays of channel-like structures and separation structures.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 08/19/2026
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