DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species 1, claims 1-5 and claim 9, in the reply filed on 08/26/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3 and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. 20230140748.
PNG
media_image1.png
256
712
media_image1.png
Greyscale
Regarding claim 1, fig. 2i of Lee discloses a semiconductor package, comprising:
a package substrate 152 having a front surface 157 and a rear surface 159, wherein the package substrate comprises:
a plurality sets of front conductive patterns 156 formed on the front surface;
a plurality sets of rear conductive patterns 156 formed on the rear surface; and
a plurality sets of interconnects (those in layer 154) electrically coupling the set of front conductive patterns with the set of rear conductive patterns, respectively;
wherein the package substrate at least comprises a first thermal performance region (region below 186) and a second thermal performance region (region below 104), wherein the first thermal performance region and the second thermal performance region have different thermal performances (different since thermal from 104 is different than thermal from 186s);
a plurality sets of conductive components attached to the front surface (set for those of 186s and set for those of 104) and the rear surface of the package substrate and connected to the plurality sets of front conductive patterns and the plurality sets of rear conductive patterns, wherein the plurality sets of conductive components comprise:
a set of first-type conductive components (solder paste – par [0024] and 190 and 200 – see fig. 2i) mounted to the first thermal performance region of the package substrate, wherein the set of first-type conductive components are connected to a portion of the front conductive patterns and the rear conductive patterns; and
a set of second-type conductive components (114 and 200 connected to 104) mounted to the second thermal performance region of the package substrate, wherein the set of second-type conductive components are connected to a portion of the front conductive patterns and the rear conductive patterns.
Regarding claim 3, fig. 2i of Lee discloses wherein the first-type conductive components are attached to the front surface and the rear surface of the package substrate in pairs.
Regarding claim 9, fig. 2i of Lee discloses wherein a density of interconnects in the second thermal performance region of the package substrate is higher than that of interconnects in a region of the package substrate outside the second thermal performance region.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Yang et al. 20220199593.
Regarding claim 2, Lee discloses claim 1, but does not discloses wherein the first-type conductive components comprise a conductive copper pillar, or a conductive solder ball having a copper core and a soldering material coating outside the copper core.
However, par [0044] of Yang discloses of a semiconductor chip 101 may be electrically connected to the package substrate 100 through a plurality of connecting elements 112 such as copper bumps.
As such it would have been obvious to form a package of Lee wherein the first-type conductive components comprise a conductive copper pillar such as taught by Yang as copper is low resistance to applicant’s resistance needs.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of SHIMIZU et al. 20160020163.
Regarding claim 4, Lee discloses claim 1, but does not discloses of wherein the second-type conductive components comprise a conductive solder ball having a resin core and a soldering material coating outside the resin core.
However, par [0218] of SHIMIZU discloses a solder ball, in which the circumference of a resin core ball is covered with solder.
As such it would have been obvious to form a package of Lee comprising wherein the second-type conductive components comprise a conductive solder ball having a resin core and a soldering material coating outside the resin core such as taught by SHIMIZU in order to a structure to prevent solder ball collapse.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lin et al. 20070194430.
Regarding claim 5, Lee discloses claim 1, but wherein the plurality sets of conductive components comprise a tin solder ball attached to a region of the package substrate outside the first thermal performance region and the second thermal performance region.
However, par [0007] of Lin discloses that chip package, which utilizes a metal lead frame to assemble the chip and to bond the wire, has the advantages of low cost, efficient heat dissipation and scale reduction for a multi-layer laminate utilizing a tin solder ball array arranged on the bottom of the multi-layer laminate substrate to increase the amount of the lead in the same area, it still has the limits in the scale reduction due to the material composition for the current electronic components, which have been developed with a smaller size and a higher density.
As such it would have been obvious to form a package of Lee comprising wherein the plurality sets of conductive components comprise a tin solder ball attached to a region of the package substrate outside the first thermal performance region and the second thermal performance region such as taught by Lin in order to save cost.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PURVIS A. Sue can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
Prosecution Insights