Prosecution Insights
Last updated: October 02, 2026
Application No. 18/740,674

SEMICONDUCTOR DEVICE INCLUDING AN INTEGRATED WAFER LEVEL HEAT SINK WINDOW PLATE

Final Rejection §102§103§112
Filed
Jun 12, 2024
Examiner
PAPE, ZACHARY
Art Unit
2841
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SanDisk Technologies Inc.
OA Round
2 (Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
808 granted / 1116 resolved
+4.4% vs TC avg
Strong +19% interview lift
Without
With
+19.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
42 currently pending
Career history
1149
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
50.4%
+10.4% vs TC avg
§102
26.9%
-13.1% vs TC avg
§112
18.0%
-22.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1116 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections The objections to claims 18-19 are withdrawn in view of the amendments thereto. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. The limitation, “heat sink means, disposed on one or more of the controller die and an uppermost memory die of the one or more memory dies, for conducting heat away from the die on which the heat sink means is disposed” is believed to meet a), b) and c) of the above-noted three-prong test. Accordingly, 112(f) is invoked with respect to this limitation. The Examiner hereby finds that the heat conductor (130) of Kang et al. (US 2019/0131203) is equivalent to the claimed heat sink means since this element of Kang et al. a) performs the function specified in the claim (The heat conductor (130) of Kang et al. conducts heat away from a die on which it is disposed), b) is not excluded by any explicit definition provided in the specification, and c) is an equivalent of the means plus function limitation. Further, the Examiner notes that the heat conductor element (130) of Kang et al. performs the identical function specified in the claim (Conducts heat away from a die on which it is mounted) in substantially the same way (Via conductive heat removal) and produces substantially the same results (Cooling of the underlying die) as the heat sink window plate disclosed in the specification. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US 2019/0131203 – hereinafter, “Kang”). With respect to claim 20, Kang teaches (In Fig 3) a semiconductor device, comprising: a substrate (500); a controller die (110) physically and electrically mounted to the substrate (See Fig 3); one or more memory dies (310) physically and electrically mounted to each other and the substrate (See Fig 3); heat sink means (130), disposed on one or more of the controller die (110) and an uppermost memory die of the one or more memory dies, for conducting heat away from the die on which the heat sink means is disposed (¶ 0040); and an encapsulant (710) for at least partially encapsulating the semiconductor device, wherein the heat sink means (130) is exposed through the encapsulant (¶ 0041, “A top surface 131 of the heat conductor 130 opposite to the first semiconductor chip 110 may be exposed to an outside region of the semiconductor package 10”). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-2, 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Bradley (US 5,308,429). With respect to claim 1, Kang teaches (In Fig 3) a semiconductor device, comprising: a substrate (500); a semiconductor controller die (110, ¶ 0023, “the first semiconductor chip 110 may correspond to a controller chip”) physically and electrically mounted to the substrate (500, see Fig 3); one or more semiconductor memory dies (310, ¶ 0023, “the third semiconductor chip 300 may include a nonvolatile memory constituting an SSD”) physically and electrically mounted to each other and the substrate (See Fig 3); one or more heat sink window plates (130), each HSWP comprising a heat sink (¶ 0041, “Thus, the heat conductor 130 may constitute a third heat conduction path 805 that transmits heat generated by the first semiconductor chip 110 to an outside region of the semiconductor package 10.”) each having first (132) and second (131) surfaces, the first surface (132) formed on one or more of a surface (111) of the controller die (110, ¶ 0041, “a bottom surface 132 of the heat conductor 130 is in contact with the top surface 111 of the first semiconductor chip 110”. Note that this limitation is a product-by-process limitation and even though the claims are limited and defined by the recited process, the determination of patentability of the product is based on the product itself, and does not depend on its method of production. If the product in the product-by-process limitation is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process1. In the present case the product of having a bottom side of a heat sink window plate mounted on a controller die is taught by Kang and thus the process of forming the plate on the die carries little patentable weight), and a surface of the uppermost memory die of the one or more memory dies; and an encapsulant (710 + 720) for at least partially encapsulating the semiconductor device, wherein the second surface (131) of the one or more HSWPs is exposed through the encapsulant (¶ 0041, “A top surface 131 of the heat conductor 130 opposite to the first semiconductor chip 110 may be exposed to an outside region of the semiconductor package 10.”). Kang fails to specifically teach or suggest each HSWP comprising a heat sink and a thermally conductive adhesive layer bonded to the heat sink, the thermally conductive adhesive layer being disposed between the heat sink and the semiconductor controller die or the uppermost semiconductor memory die. Bradley, however, teaches (In Fig 1) a thermal conductor which includes a heat sink (30) and a thermally conductive adhesive layer (33) bonded to the heat sink, the thermally conductive adhesive layer being disposed between the heat sink and a semiconductor chip package (20, see Fig 1). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bradley with that of Kang such that, in Kang each HSWP comprising a heat sink and a thermally conductive adhesive layer bonded to the heat sink, the thermally conductive adhesive layer being disposed between the heat sink and the semiconductor controller die, as taught by Bradley, since doing so would provide for good thermal contact between the top of the die and the bottom of the heat sink. With respect to claim 2, Kang further teaches wherein the controller die (110) comprises a plurality of bump bonds (161) for flip-chip mounting the controller die to the substrate, a first HSWP (130) of the one or more HSWPs mounted on an inactive surface (Top surface) of the controller die (110, see Fig 3). With respect to claim 8, even though the claims are limited and defined by the recited process, the determination of patentability of the product is based on the product itself, and does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In the present case, as per the above rejection to claim 1, Kang anticipates the claimed apparatus and thus the process of forming the apparatus, as claimed in claim 8, carries little patentable weight. With respect to claim 9, Kang further teaches wherein an HSWP (130) of the one or more HSWPs is affixed to the controller die (110, see Fig 3). With respect to the limitations wherein the HSWP and controller die are diced from a combined wafer including a plurality of HSWPs and a plurality of controller dies, even though the claims are limited and defined by the recited process, the determination of patentability of the product is based on the product itself, and does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In the present case, as per the above rejection to claims 1 and 9, Kang anticipates the claimed apparatus and thus the process of forming the apparatus, as claimed in a portion of claim 9, carries little patentable weight. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Bradley in view of Xu et al. (US 2023/0137512 – hereinafter, “Xu”) and further in view of Her et al. (US 2002/0180023 – hereinafter, “Her”). With respect to claim 3, Kang as modified by Bradley teaches the limitations of claim 1 as per above but fails to specifically teach or suggest, wherein the uppermost memory die comprises a die attach film layer for mounting the memory die to the substrate, a second HSWP of the one or more HSWPs mounted on an active surface of the memory die. Xu, however, teaches wherein an uppermost memory die (120) comprises a die attach film layer for mounting the memory die to a substrate (¶ 0039, “The dies 120 may be affixed to the substrate and/or each other using a die attach film”). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Xu with that of Kang such that the uppermost die comprises a die attach fil layer for mounting the memory die to the substrate, as taught by Xu, since doing so would allow for the memory die to be securely affixed to the substrate which would prevent it from moving relative to the substrate during, for example, shipping. With respect to the limitations which require a second HSWP of the one or more HSWPs mounted on an active surface of the memory die, Her teaches (In Fig 5) a second HSWP (520b+504), the HSWP including a heat sink (520b) and a thermally conductive adhesive (504), the second HSWP of one or more HSWPs mounted on an active surface of a chip (508). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Her with that of Kang such that, in Kang, a second HSWP of the one or more HSWPs mounted on an active surface of the memory die, as taught by Her, since doing so would allow for the memory die to be cooled thus increasing the life and reducing failure of the memory die. Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Bradley in view of Yin et al. (TW M655625 – hereinafter, “Yin”) and further in view of Long et al. (US 2024/0105544 – hereinafter, “Long”). With respect to claims 4-7, Kang as modified by Bradley teaches the limitations of claim 1 as per above but fails to specifically teach or suggest the limitations of claims 4-7. Yin, however teaches an HSWP (a heat spreader) comprised of a plurality of sublayers, wherein a first sublayer (100) of the HSWP is comprised of Copper, wherein a third sublayer (200) of the HSWP is comprised of Nickel and a fourth sublayer (300) of the HSWP is comprised of Chromium (“the structure of the copper foil composite heat spreader of the present invention, which includes a copper foil base layer 100, a nickel-containing metal layer 200 and a chromium-containing metal layer 300”). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yin with that of Kang such that, in Kang an HSWP of the one or more HSWPs is comprised of a plurality of sublayers, wherein a first sublayer of the HSWP is comprised of Copper, wherein a third sublayer of the HSWP is comprised of Nickel and a fourth sublayer of the HSWP is comprised of Chromium, as taught by Yin, since doing so would provide a heat sink window plate that is protected from corrosion, oxidation, and tarnishing. With respect to the limitations that a second sublayer of the HSWP is comprised of a thermally conductive adhesive, Long teaches a thermally conductive adhesive (112) which is a layer on a heat sink window plate (118). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the further teachings of Long with that of Kang as modified by Yin such that the heat sink window plate of modified Kang further includes a layer of thermally conductive adhesive, as taught by Long, since doing so would thermally and mechanically bond the HSWP of Kang to the semiconductor controller die. Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Bradley and further in view of Long. With respect to claim 10, Kang as modified by Bradley teaches the limitations of claim 1 as per above but fails to specifically teach or suggest wherein an HSWP of the one or more HSWPs is affixed to the memory die, and wherein the HSWP and memory die are diced from a combined wafer including a plurality of HSWPs and a plurality of memory dies. Long, however, teaches (In Fig 1) a first die (104) with a first HSWP (114) and a second die (106) and a second HSWP (118) of the one or more HSWPs is affixed to the second die (106). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Long with that of Kang such that, in Kang a second HSWP is affixed to the memory die (310), as taught by Long, since doing so would provide heat dissipation to the memory die. With respect to the limitations wherein the HSWP and memory die are diced from a combined wafer including a plurality of HSWPs and a plurality of memory dies, even though the claims are limited and defined by the recited process, the determination of patentability of the product is based on the product itself, and does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In the present case, as per the above rejection to claims 1 and 10, Kang, Bradley and Long obviate the claimed apparatus and thus the process of forming the apparatus, as claimed in a portion of claim 10, carries little patentable weight. With respect to claims 11-12, Kang as modified by Bradley teaches the limitations of claim 1 as per above but fails to specifically teach or suggest wherein both of the controller die and the one or more memory dies have an HSWP of the one or more HSWPs affixed to its surface, wherein the exposed second surface of the HSWP on the controller die is coplanar with the exposed second surface of the HSWP on the memory die. Long, however, teaches (In Fig 1) a first die (104) with a first HSWP (114) affixed thereon which has a surface exposed from an encapsulant (120) and a second die (106) with a second HSWP (118) affixed thereon which has a surface exposed from the encapsulant (120), wherein the exposed surface of the first HSWP (114) is coplanar with the exposed surface of the second HSWP (118, see Fig 1). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Long with that of Kang such that, in Kang both of the controller die and the one or more memory dies have an HSWP of the one or more HSWPs affixed to its surface, wherein the exposed second surface of the HSWP on the controller die is coplanar with the exposed second surface of the HSWP on the memory die. Allowable Subject Matter Claims 13-19 are allowed. The following is an examiner’s statement of reasons for allowance: With respect to claim 13, the allowability resides in the overall structure of the device as recited in independent claim 13 and at least in part because claim 13 recites, “a second wafer comprising a plurality of heat sink window plates, each HSWP of the plurality of HSWPs comprising a heat sink and a thermally conductive adhesive; wherein the first wafer is aligned with the second wafer such that the plurality of integrated circuit dies align with the plurality of HSWPs; and wherein the aligned first and second wafers are coupled to each other by the thermally conductive adhesive on each HSWP”. The aforementioned limitations in combination with all remaining limitations of claim 13 are believed to render said claim 13 and all claims dependent therefrom patentable over the art of record. The closest art of record is believed to be that of Chen (CN 109216301) which teaches a combination semiconductor wafer, comprising: a first wafer (102) comprising a plurality of integrated circuit dies (101); a second wafer (105) comprising a heat sink window plate (114), wherein the first wafer (105) is aligned with the second wafer (102, see Fig 7E). Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments With respect to the Applicant’s remarks to claim 1 that, “Applicant has amended the claims to clarify the distinctions between the Kang and the present invention. For example, independent claim 1 as amended recites in part: one or more heat sink window plates (HSWPs), each HSWP comprising a heat sink and a thermally conductive adhesive layer bonded to the heat sink, the thermally conductive adhesive layer being disposed between the heat sink and the semiconductor controller die or the uppermost semiconductor memory die, each HSWP having first and second surfaces, the first surface formed on one or more of a surface of the controller die and a surface of the uppermost memory die of the one or more memory dies. These features are not disclosed in Kang.” (Present remarks page 6) the Examiner agrees and notes the previous 102(a) rejection to claim 1 is withdrawn. However, a new grounds rejection is provided above in view of Kang and Bradley where Bradley is believed to cure the deficiency in Kang. Indeed, Bradley teaches the conventionality of placing a thermally conductive adhesive layer between a heat sink and a component to increase heat transfer away from a component. Thus, claim 1 is believed to be prima facie obvious in view of Kang and Bradley. With respect to the Applicant’s remarks to claim 20 that, “Claim 20 is likewise patentable over Kang. Claim 20 recites in part: heat sink means ... for conducting heat away from the die on which the heat sink means is disposed. Because the claim employs the term "means" together with functional language, the limitation is interpreted under 35 U.S.C. § 112(f). Accordingly, the claimed "heat sink means" is not broad enough to encompass every structure capable of conducting heat away from a semiconductor die. Rather, the limitation is construed to cover the corresponding structure described in the Specification and equivalents thereof. The corresponding structure disclosed in applicant's specification is a heat sink window plate (HSWP). The specification does not describe the HSWP as merely a heat-conductive member positioned on a semiconductor die. Rather, the HSWP is disclosed as a specific composite structure that includes both a heat sink and a thermally conductive adhesive layer that is part of the HSWP itself. The thermally conductive adhesive layer is bonded to the heat sink and is disposed between the heat sink and the semiconductor die, thereby forming an integrated HSWP that is incorporated into the semiconductor package. The Office Action identifies Kang's heat conductor 130 as corresponding to the claimed heat sink means. However, Kang's heat conductor 130 is simply a heat-conductive member. Kang nowhere discloses that heat conductor 130 is itself a composite structure including both a heat sink and a thermally conductive adhesive layer, nor does Kang disclose that an adhesive layer forms part of the heat-conductive member itself. At most, Kang discloses a separate heat conductor positioned above a semiconductor chip. The structure disclosed by Kang is therefore materially different from the HSWP disclosed in Applicant's Specification, which defines the corresponding structure for the claimed means-plus-function limitation. The Office Action effectively treats the claimed "heat sink means" as encompassing any generic heat-conductive member capable of removing heat from a semiconductor die. Respectfully, that is not the proper analysis under § 112(f). The proper inquiry is whether Kang discloses the corresponding structure described in the specification, or an equivalent thereof. Because Kang discloses only a conventional heat conductor, and not the HSWP structure disclosed in applicant's specification, Kang fails to disclose the claimed "heat sink means." (Present remarks pages 7-8) the Examiner respectfully disagrees. As noted above, under 112(f), the limitations, “heat sink means, disposed on one or more of the controller die and an uppermost memory die of the one or more memory dies, for conducting heat away from the die on which the heat sink means is disposed” can be met either by the corresponding structure described in the specification or equivalents thereof. It is respectfully submitted that a prima facie case of equivalence was made by the Examiner on page 5 of the non-final office action. The same case of equivalence is reiterated above on pages 4-5 of the present detailed action. Accordingly, Kang is believed to teach a prima facie equivalent structure to that being described in the specification and claim 20 is believed to be properly anticipated by Kang. With respect to the Applicants’ additional remarks to the dependent claims (Present remarks pages 8-9) the Examiner respectfully notes that, since the remarks regarding independent claim 1 are not found to be persuasive, and since there are no additional persuasive remarks provided with respect to the dependent claims, the dependent claims are believed to be properly rejected. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZACHARY M PAPE whose telephone number is (571)272-2201. The examiner can normally be reached M-F: 9am - 6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JAYPRAKASH Gandhi can be reached at 571-272-3740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ZACHARY PAPE/Primary Examiner, Art Unit 2841 1 In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985).
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Prosecution Timeline

Jun 12, 2024
Application Filed
May 07, 2026
Non-Final Rejection mailed — §102, §103, §112
Jul 29, 2026
Response Filed
Aug 13, 2026
Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
92%
With Interview (+19.4%)
2y 5m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
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