Prosecution Insights
Last updated: October 22, 2026
Application No. 18/740,705

ELECTRO-MIGRATION REDUCTION

Non-Final OA §102§DOUBLEPATENT
Filed
Jun 12, 2024
Priority
May 29, 2020 — provisional 63/032,467 +2 more
Examiner
KUSUMAKAR, KAREN M
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
862 granted / 987 resolved
+19.3% vs TC avg
Moderate +10% lift
Without
With
+9.8%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
16 currently pending
Career history
1001
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
44.9%
+4.9% vs TC avg
§102
37.6%
-2.4% vs TC avg
§112
8.5%
-31.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 987 resolved cases

Office Action

§102 §DOUBLEPATENT
DETAILED ACTION Information Disclosure Statement The information disclosure statements (IDS) submitted on 6/12/24 and 8/27/24 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1, 2, 5-7, 9-11, and 15-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent Nos. 12,014,987 and 11,450,609 as detailed below. Although the claims at issue are not identical, they are not patentably distinct from each other for the reasons stated below. Instant claims ‘987 claims ‘609 claims reasoning 1 16 8 The instant claims are broader than those of the ‘987 and ‘609 patents, thus they are anticipated. 2 19 11 anticipated 5 16 8 anticipated 6 20 12 Substantially similar 7 16 8 anticipated 9 16 8 anticipated 10 19 11 The instant claims are broader than those of the ‘987 and ‘609 patents, thus they are anticipated. 11 19 11 anticipated 15 20 12 Substantially similar 16 19 8 anticipated 17 16 8 The instant claims are broader than those of the ‘987 and ‘609 patents, thus they are anticipated. 18 20 12 Substantially similar Allowable Subject Matter Claims 1-20 are subject to a double patenting (DP) rejection, but would be allowable if the outstanding DP rejection is overcome. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper. The prior art fails to teach a combination of all of the features in the claims. As to claim 1, 10, and 17, Chi (US 2015/0123279) teaches a contact structure (Fig. 7b), comprising: a conductive feature (170) disposed in a first dielectric layer (120); a barrier layer (140) disposed between the conductive feature (170) and the first dielectric layer (120); a metal cap layer (177) disposed on top surfaces of the conductive feature (170) and the barrier layer (140); an adhesion layer (178) disposed on the first dielectric layer (120); a dielectric capping layer (180) disposed over the metal cap layer (177) and the adhesion layer (178), and a second dielectric layer (not shown but obvious that there would/could be more ILD layers) disposed over the dielectric capping layer (180), Chi fails to teach: The dielectric capping layer (180) interfacing the metal cap layer (177) and the adhesion layer (178) (the adhesion layer 178 covers the metal cap 177, thus there is no interface between the dielectric capping layer 180 and the metal cap 177). the dielectric capping layer (180) comprises aluminum nitride or boron nitride (it is a standard ILD layer, which is not necessarily assumed to be aluminum nitride or boron nitride without some motivation). the adhesion layer comprises hexagonal beta silicon nitride (not taught). As to claim 1, 10, and 17, Lee (US 12,400,911) teaches a contact structure (Fig. 3), comprising: a conductive feature (113) disposed in a first dielectric layer (150); a barrier layer (111/112) disposed between the conductive feature (113) and the first dielectric layer (150); a metal cap layer (114) disposed on top surfaces of the conductive feature (113) and the barrier layer (111/112); an adhesion layer (155) disposed on the first dielectric layer (150); a dielectric capping layer (1860) disposed over the metal cap layer (114) and the adhesion layer (1155), and a second dielectric layer (not shown but obvious that there would/could be more ILD layers) disposed over the dielectric capping layer (160). Lee fails to teach: The dielectric capping layer (160) interfacing the metal cap layer (114) and the adhesion layer (155) (the adhesion layer 155 covers the metal cap 114, thus there is no interface between the dielectric capping layer 160 and the metal cap 114). the dielectric capping layer (160) comprises aluminum nitride or boron nitride (it is a standard ILD layer, which is not necessarily assumed to be aluminum nitride or boron nitride without some motivation). the adhesion layer comprises hexagonal beta silicon nitride (silicon nitride is taught but not hexagonal beta silicon nitride). The remaining claims are allowable at least because they depend from allowable independent claims. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any response to this Office Action should be faxed to (571) 273-8300 or mailed to: Commissioner for Patents P.O. Box 1450 Alexandria, VA 22313-1450 Hand-Delivered responses should be brought to: Customer Service Window Randolph Building 401 Dulany Street Alexandria, VA 22313 Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KAREN KUSUMAKAR/ Primary Examiner, Art Unit 2897 10/11/26
Read full office action

Prosecution Timeline

Jun 12, 2024
Application Filed
Oct 14, 2026
Non-Final Rejection mailed — §102, §DOUBLEPATENT (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 11m to grant Granted Oct 20, 2026
Patent 12765239
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3y 0m to grant Granted Oct 13, 2026
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2y 8m to grant Granted Oct 13, 2026
Patent 12757477
SEMICONDUCTOR DIE WITH A VERTICAL DEVICE
2y 6m to grant Granted Oct 06, 2026
Patent 12757583
DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME
2y 6m to grant Granted Oct 06, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
97%
With Interview (+9.8%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 987 resolved cases by this examiner. Grant probability derived from career allowance rate.

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