DETAILED ACTION
This Office Action is in response to Applicant’s application 18/740,726 filed on June 12, 2024 in which claims 1 to 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on June 12, 2024 have been reviewed and accepted by the Examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 12,050,966 (‘966) . Although the claims at issue are not identical, they are not patentably distinct from each other as discussed below.
Table 1 – Comparison of Pending Claims to ‘966 Claims
Pending Claim
‘966
1. An integrated circuit (IC) structure, comprising:
a quantum well stack;
a plurality of gates over the quantum well stack; and
a microcoil arrangement over the quantum well stack, the microcoil arrangement comprising:
an elongated structure comprising a ferromagnetic material or a ferrimagnetic material, and
a winding structure comprising one or more conductive materials,
the winding structure winding around the elongated structure with a plurality of turns.
1. A quantum dot device, comprising:
a support structure;
a quantum well stack over the support structure, the quantum well stack including a quantum dot formation region;
a plurality of gates over the support structure, the plurality of gates extending to the quantum dot formation region; and
a microcoil arrangement over the support structure, the microcoil arrangement proximate to the plurality of gates and including:
a core comprising a ferromagnetic material or a ferrimagnetic material having an elongated shape, and
a microcoil comprising an electrically conductive material, the
microcoil winding around the core with a plurality of turns.
2. The IC structure according to claim 1, wherein a shape of the winding structure is substantially a helix or a coil.
2. The quantum dot device according to claim 1, wherein a shape of the microcoil is substantially a helix or a coil.
3. The IC structure according to claim 1, wherein a length of the elongated structure is between about 100 nanometers and 1000 microns.
3. The quantum dot device according to claim 1, wherein a length of the core is between about 100 nanometers and 1000 microns.
4. The IC structure according to claim 3, wherein an area of a cross-section of the elongated structure in a plane substantially perpendicular to a longitudinal axis of the elongated structure is between about 0.052 and 1002 square micron.
4. The quantum dot device according to claim 3, wherein an area of a cross-section of the core in a plane substantially perpendicular to a longitudinal axis of the core is between about 0.052 and 1002 square microns.
5. The IC structure according to claim 1, wherein an average distance between the winding structure and the elongated structure is between about 1 nanometer and 20 microns.
5. The quantum dot device according to claim 1, wherein an average distance between the microcoil and the core is between about 1 nanometer and 20 microns.
6. The IC structure according to claim 1, further comprising an insulator between the winding structure and the elongated structure.
6. The quantum dot device according to claim 1, further comprising an insulating material between the microcoil and the core.
7. The IC structure according to claim 1, wherein an individual turn of the plurality of turns of the winding structure includes: a first conductive line at a first distance from the quantum well stack, a second conductive line at a second distance from the quantum well stack and offset with respect to the first conductive line, where the first distance is larger than the second distance and where an individual one of the first conductive line and the second conductive line has a first end and an opposing second end, a first conductive via having a first end in conductive contact with the first end of the first conductive line and having a second end in conductive contact with the first end of the second conductive line, and a second conductive via having a first end in conductive contact with the second end of the first conductive line and having a second end in conductive contact with the second end of the second conductive line.
7. The quantum dot device according to claim 1, wherein an individual turn of the plurality of turns of the microcoil includes: a first conductive line at a first distance from the support structure, a second conductive line at a second distance from the support structure and offset with respect to the first conductive line, where the first distance is larger than the second distance and where an individual one of the first conductive line and the second conductive line has a first end and an opposing second end, a first conductive via having a first end in conductive contact with the first end of the first conductive line and having a second end in conductive contact with the first end of the second conductive line, and a second conductive via having a first end in conductive contact with the second end of the first conductive line and having a second end in conductive contact with the second end of the second conductive line.
8. The IC structure according to claim 7, wherein a height of the first conductive via or the second conductive via is between about 10 nanometers and 100 microns.
8. The quantum dot device according to claim 7, wherein a height of the first conductive via or the second conductive via is between about 10 nanometers and 100 microns.
9. The IC structure according to claim 7, wherein the first conductive via or the second conductive via are substantially perpendicular to the quantum well stack.
9. The quantum dot device according to claim 7, wherein the first conductive via and the second conductive via are substantially perpendicular to the support structure.
10. The IC structure according to claim 7, wherein a length of the first conductive line or the second conductive line is between about 50 nanometers and 1000 microns.
10. The quantum dot device according to claim 7, wherein a length of the first conductive line or the second conductive line is between about 50 nanometers and 1000 microns.
11. The IC structure according to claim 7, wherein a distance between a projection of the first conductive line and a projection of the second conductive line onto a plane parallel to the quantum well stack is below about 10 microns.
11. The quantum dot device according to claim 7, wherein a distance between a projection of the first conductive line and a projection of the second conductive line onto a plane parallel to the support structure is below about 10 microns.
12. The IC structure according to claim 1, wherein:
the quantum well stack has a first face and a second face opposite the first face,
the plurality of gates is over the first face of the quantum well stack, and the
microcoil arrangement is over the second face of the quantum well stack.
12. The quantum dot device according to claim 1, wherein:
the support structure has a first face and an opposing second face,
the quantum well stack and the plurality of gates are over the first face of the support structure, and the
microcoil arrangement is over the second face of the support structure.
13. The IC structure according to claim 1, wherein the quantum well stack has a first face and a second face opposite the first face, and the plurality of gates and the microcoil arrangement are over the first face of the quantum well stack.
13. The quantum dot device according to claim 1, wherein the support structure has a first face and an opposing second face, and the quantum well stack, the plurality of gates, and the microcoil arrangement are over the first face of the support structure.
14. The IC structure according to claim 1, wherein: the quantum well stack has a first face and a second face opposite the first face, the microcoil arrangement is a first microcoil arrangement of a plurality of microcoil arrangements over the quantum well stack, the plurality of gates and the first microcoil arrangement are over the first face of the quantum well stack, and a second microcoil arrangement of the plurality of microcoil arrangements is over the second face of the quantum well stack.
14. The quantum dot device according to claim 1, wherein: the support structure has a first face and an opposing second face, the microcoil arrangement is a first microcoil arrangement of a plurality of microcoil arrangements over the support structure, the quantum well stack, the plurality of gates, and the first microcoil arrangement are over the first face of the support structure, and a second microcoil arrangement of the plurality of microcoil arrangements is over the second face of the support structure.
15. A quantum computing device, comprising:
a quantum processing device, comprising
a plurality of qubits,
a plurality of gates coupled to individual ones of the plurality of qubits, and
a microcoil arrangement proximate to the plurality of qubits; a
non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the plurality of gates; and a
memory device to store data generated during operation of the quantum processing device.
15. A quantum computing device, comprising:
a quantum processing device, comprising
a plurality of spin qubits,
a plurality of gates coupled to individual ones of the plurality of spin qubits, and
a microcoil arrangement to generate a magnetic field for manipulating the plurality of spin qubits;
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the plurality of gates; and
a memory device to store data generated during operation of the quantum processing device.
16. The quantum computing device according to claim 15, wherein the microcoil arrangement includes:
an elongated structure that includes a ferromagnetic material or a ferrimagnetic material, and
a conductive arrangement comprising conductive lines and vias in conductive contact with one another,
wherein the conductive arrangement wraps around the elongated structure.
16. The quantum computing device according to claim 15, wherein the microcoil arrangement includes:
an elongated core that includes a ferromagnetic material or a ferrimagnetic material, and
conductive lines and vias, arranged in conductive contact with one another
along a substantially helical contour around the elongated core.
17. The quantum computing device according to claim 16, wherein the conductive lines and vias follow a substantially helical contour around the elongated structure.
conductive lines and vias, arranged in conductive contact with one another along a substantially helical contour around the elongated core.
18. The quantum computing device according to claim 15, wherein the microcoil arrangement includes: a core comprising a ferromagnetic material or a ferrimagnetic material, and
a conductive arrangement wrapping around the core in a plurality of turns.
16. The quantum computing device according to claim 15, wherein the microcoil arrangement includes: an elongated core that includes a ferromagnetic material or a ferrimagnetic material, and
conductive lines and vias, arranged in conductive contact with one another along a substantially helical contour around the elongated core.
19. An integrated circuit (IC) structure, comprising:
a quantum well stack;
a plurality of gates over the quantum well stack;
an elongated structure proximate to plurality of gates, the elongated structure
comprising a ferromagnetic material or a ferrimagnetic material; and
a winding structure comprising one or more conductive materials, the winding structure winding around the elongated structure.
1. A quantum dot device, comprising:
a support structure;
a quantum well stack over the support structure, the quantum well stack including a quantum dot formation region;
a plurality of gates over the support structure, the plurality of gates extending to the quantum dot formation region; and
a microcoil arrangement over the support structure, the microcoil arrangement proximate to the plurality of gates and including:
a core comprising a ferromagnetic material or a ferrimagnetic material having an elongated shape, and
a microcoil comprising an electrically conductive material, the
microcoil winding around the core with a plurality of turns.
20. The IC structure according to claim 19 further comprising an insulator between the winding structure and the elongated structure.
6. The quantum dot device according to claim 1, further comprising an insulating material between the microcoil and the core.
Regarding claim 1 and referring to Table 1, Examiner notes each claim recites a quantum well structure. Pending claim requires gates of the quantum well structure which appears to also describe the condition of gates that are over a over a support structure on which a quantum well structure is positioned where the gates extend to the quantum well structure which in turn comprises quantum dots. A core with an elongated structure appears to be a species of a generic elongated structure. Likewise a micro coil appears to be a species of a winding structure. Lastly the micro coil or winding structure comprises turns. Thus, it appears to Examiner that the scope of claim 1 is greater than the scope of claim 1 of the ‘966 patent.
Regarding claims 2-11, it appears this subject matter is described in claim 2-11 of the ‘966 patent.
Regarding claim 12, it appears pending claim 12 and claim 12 of the ‘966 patent both describe the condition of gates on the top of the quantum well and the winding structure under the quantum well.
Regarding claim 13, it appears pending claim 13 and claim 13 of the ‘966 patent both describe the arrangement of quantum wells below gates which are in turn below the winding structure.
Regarding claim 14, it appears pending claim 14 and claim 14 of the ‘966 patent both describe a plurality of quantum well/gate stacks with the winding structure alternating between the top of bottom of adjacent quantum well/gate stacks.
Regarding claim 15, it appears that a spin qubit is a species of qubit and that the structure of pending claim 15 is described in claim 15 of the ‘966 patent.
Regarding claim 16, it appears that lines wrapping around an elongated structure is within the scope lines with a helical contour around an elongated core.
Regarding claim 17, claim 16 of the ‘966 patent explicitly describes a helical contour of conducive lines wrapping around an elongated core.
Regarding claim 18, claim 16 of the ‘966 patent recites an elongated core which appears to be a species of core. Likewise conductive lines and vias appear to be a species of a conductive structure both of which wrap around the core.
Regarding claim 19 and referring to Table 1, and elongate structure proximate to gates, appears to describe or be within the scope of, the structure of a micro-coil having a core of an elongated shape and windings around the core.
Regarding claim 20, claim 6 of the ‘966 patent describes this subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893