DETAILED ACTION
This action is responsive to the Amendments filed March 2, 2026. Prior to entry, claims 1-11 were pending. Claim 1 has been amended. Claim 5 has been cancelled. Therefore, upon entry, claims 1-4 and 6-11 are pending. Claims 1 and 7 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Memory Device with Multiple Planes and Distributed Microcontroller Control.
Claim Rejections - 35 USC § 112 – Improper Form
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 6 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 6 depends from base claim 5 which has been cancelled and therefore claim 6 is incomplete (see MPEP § 608.01(n) Sect. V). Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 20220180916 – of Record) in view of Hsu et al. (US 20190179573; "Hsu").
Regarding independent claim 1, Chung discloses a memory comprising:
a plurality of planes (Fig. 2 where it illustrates planes within the memory array. See also para. 36; "The memory cell array 110 may include planes PL1 to PLk (k is a positive integer) in which data is stored");
and a plurality of microcontrollers (Fig. 3 where it illustrates microcontrollers M1-Mk. See also para. 50; "The first to k-th micro-control circuits M1 to Mk may be circuits included in the micro-control circuit group 350 and may be configured to control the first to k-th planes PL1 to PLk, respectively"),
Chung is silent about more than one controller performing a control operation on the same plane.
However, Hsu teaches wherein, during a specific operation of a selected plane, among the plurality of planes, at least two microcontrollers, among the plurality of microcontrollers, perform a distributed execution of control operations on the selected plane (Fig. 10A where it illustrates a first processor 1002 and a second processor 1004 simultaneously operating on a selected memory plane 126. See also para. 26; "The processors in one embodiment of the microcontroller may execute in parallel, which is more efficient and reduces overhead. For example, during program or read operations, each of the processors may have different functions.").
wherein the control operations include
a bias control operation that controls generation of various operating voltages (Fig. 10A, voltage generator 1024),
a page buffer control operation that controls a page buffer (Fig. 10A, sensing circuit 1026),
a control operation of a row circuit to control row lines (Fig. 10A, row decoder 128),
and a logic control operation that controls a flow of the bias control operation, page buffer control operation, and control operation of the row circuit (Fig. 10B where it illustrates main processor 1006 controlling the (flow of the) other two processors),
and wherein the at least two microcontrollers perform different ones of the control operations, respectively (Figs. 13 and 14 which illustrate the function and flow of the various processors executing different parts of the control operation on the memory plane simultaneously).
Chung and Hsu are from the same field of endeavor as applicant’s invention directed to operation of multi-plane memory arrays with microcontrollers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chung’s memory array structure with the teachings of Hsu’s multiple parallel processors (controllers) to operate on the same memory plane. Doing so would improve single plane memory operations by making them more efficient.
Regarding claim 2, Chung and Hsu combined disclose the limitations of claim 1.
As applied, Hsu further discloses wherein the specific operation includes one or more of a program operation, an erase operation, and a read operation (para. 175; "Process 1400 shows how the various processors 1002, 1004, 1006 can work in parallel during one embodiment of a program operation").
Regarding claim 3, Chung and Hsu combined disclose the limitations of claim 1.
As applied, Chung further discloses wherein, during a parallel operation of the plurality of planes, the plurality of microcontrollers perform the control operations on the plurality of planes, respectively (para. 50; "The first to k-th micro-control circuits M1 to Mk may be circuits included in the micro-control circuit group 350 and may be configured to control the first to k-th planes PL1 to PLk, respectively. See also para. 49; "The memory device MD including the plurality of planes PL1 to PL4 may simultaneously perform the read, program, or erase operation on the memory blocks or pages positioned in different planes")
Regarding claim 4, Chung and Hsu combined disclose the limitations of claim 3.
As applied, Chung further discloses wherein the parallel operation includes a multi-plane interleaved read operation (Figs. 9A to 9E where it illustrates a plane interleaved operation over 4 planes. See also para. 84; "FIGS. 9A to 9E are diagrams illustrating a method of outputting control codes for sequentially performing read operations of a plurality of planes according to an embodiment of the present disclosure").
Regarding independent claim 7, Chung discloses a memory comprising:
a plurality of planes (Fig. 2 where it illustrates planes within the memory array. See also para. 36; "The memory cell array 110 may include planes PL1 to PLk (k is a positive integer) in which data is stored");
and a plurality of microcontrollers (Fig. 3 where it illustrates microcontrollers M1-Mk. See also para. 50; "The first to k-th micro-control circuits M1 to Mk may be circuits included in the micro-control circuit group 350 and may be configured to control the first to k-th planes PL1 to PLk, respectively"),
Chung is silent about more than one controller performing a control operation on the same plane simultaneously.
However, Hsu teaches wherein each of the plurality of planes includes:
a cell array (Fig. 1A);
a voltage generation circuit (Fig. 10A, voltage generator 1024);
a row circuit suitable for controlling row lines of the cell array by using voltages generated by the voltage generation circuit (Fig. 10A, row decoder 128);
and a page buffer array suitable for sensing data by using column lines of the cell array and controlling the column lines of the cell array to program data into the cell array (Fig. 10A, sensing circuit 1026),
wherein, during a specific operation of a selected plane, among the plurality of planes, at least two microcontrollers, among the plurality of microcontrollers, perform distributed control over the voltage generation circuit, row circuit, and page buffer array of the selected plane. (Fig. 10A where it illustrates a first processor 1002 and a second processor 1004 simultaneously operating on a selected memory plane 126. See also para. 26; "The processors in one embodiment of the microcontroller may execute in parallel, which is more efficient and reduces overhead. For example, during program or read operations, each of the processors may have different functions.").
Chung and Hsu are from the same field of endeavor as applicant’s invention directed to operation of multi-plane memory arrays with microcontrollers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chung’s memory array structure with the teachings of Hsu’s multiple processors (controllers) to operate on the same memory plane. Doing so would improve single plane memory operations by making them more efficient.
Regarding claim 8, Chung and Hsu combined disclose the limitations of claim 7.
As applied, Hsu further discloses wherein the specific operation includes one or more of a program operation, an erase operation, and a read operation (para. 175; "Process 1400 shows how the various processors 1002, 1004, 1006 can work in parallel during one embodiment of a program operation").
Regarding claim 9, Chung and Hsu combined disclose the limitations of claim 7.
As applied, Chung further discloses wherein, during a parallel operation of the plurality of planes, the plurality of microcontrollers perform control operations on the plurality of planes, respectively (para. 50; "The first to k-th micro-control circuits M1 to Mk may be circuits included in the micro-control circuit group 350 and may be configured to control the first to k-th planes PL1 to PLk, respectively. See also para. 49; "The memory device MD including the plurality of planes PL1 to PL4 may simultaneously perform the read, program, or erase operation on the memory blocks or pages positioned in different planes").
Regarding claim 10, Chung and Hsu combined disclose the limitations of claim 9.
As applied, Chung further discloses wherein the parallel operation includes a multi-plane interleaved read operation (Figs. 9A to 9E where it illustrates a plane interleaved operation over 4 planes. See also para. 84; "FIGS. 9A to 9E are diagrams illustrating a method of outputting control codes for sequentially performing read operations of a plurality of planes according to an embodiment of the present disclosure").
Regarding claim 11, Chung and Hsu combined disclose the limitations 10.
As applied, Chung further discloses wherein the at least two microcontrollers include first to fourth microcontrollers (Fig. 3 where it illustrates 4 memory planes (PL1-PLk) controlled by 4 micro-control circuits (M1 to Mk). However, it is noted that the term microcontroller is not explicitly defined in the instant application. Therefore, the term will be understood using the broadest reasonable interpretation to mean simply a control circuit. In this context, Chung's 64 scheduler (see Fig. 6) is also considered a microcontroller),
and wherein the first microcontroller controls the voltage generation circuit of the selected plane, the second microcontroller controls the row circuit of the selected plane, the third microcontroller controls the page buffer array of the selected plane (See Fig. 9E where all the microcontrollers are shown performing all the control codes for all operations),
and the fourth microcontroller controls an operational flow of the first to third microcontrollers (Fig. 6: 64 scheduler is effectively the "fourth microcontroller' in this embodiment as it generates the signals SLS and CTS# which control the timing (start and stop) of the other operation control codes. It is noted that the specification of the instant application defines the "logic control operation" only as "an operation that controls the flow of the entire operation" (para. 32) and "That is, the microcontroller 451 may control when the microcontrollers 452 to 454 have to start and end their operations." (para. 43)).
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive because, while the applicant's contention on pg. 6 of Remarks that the amendments to independent claim 1 which narrowed the claim scope are not disclosed by the previously applied references, new facts of the applied prior art combined with a new reference cause the claim to remain unpatentable under a new ground of rejection.
Applicant contends on pg. 6 of Remarks that the obviousness rejection of independent claim 7 is improper because the previously applied references fail to teach or suggest all the limitations of the claim. Further consideration and search resulting in a newly applied reference combined with a previously applied reference form a new ground of rejection substantially similar to that of claim 1.
Applicant's comments also contain statements on independent claims 12, 16 and 18 on pg. 6-7 of Remarks which appear to be a minor clerical error as they are not relevant to the claims as currently presented. As such, they are disregarded and do not overcome any matter of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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