DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 05/09/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
Figures 1A, 1B, 2, 3A, 3B, 4A, 4B, 5A, 6A, 6B, 6C, 6D, 7A, 7B, 8A, 8B should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
Instant application Figures 1A, 1B, 2, 3A, 3B, 4A, 4B, 5A, 6A, 6B, 6C, 6D, 7A, 7B are identical toSanDisk’s previously published patent No. 11,848,059 B2; US 12,354,682 B2 (as show in Figs. 7A, 7B); US 9,466,369 B1 (as show in Figs. 7-8).
These references have been added to form PTO-892 to reflect consideration. Applicant is reminded of the helpful scenarios in MPEP 2004, such as scenario 7 (characterizing information), and MPEP 2011(on how to correct the record).
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it uses the phrase “discloses”, “comprising” in page 1, line 1, which is implied. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 1-7’s “control circuit” that is “configured to” perform recited operations;
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claims 15-20, the claimed limitation “means for using…the loop”; and “means for using…other loop” is a means (or step) plus function limitation that invokes 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Blocks are not shown in enough detail to warrant protection under 35 U.S.C. 112(f). A generic box with a label does not sufficiently describe the underlying structure that performs the recited function.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f);
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Zainuddin et al (US 12,046,314 B2 hereinafter “Zainuddin”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Zainuddin, for example in Figs. 1-22, discloses an apparatus (see for example in Figs. 1A, 3A related in Figs. 2, 4-22), comprising: a plurality of memory cells (e.g., memory array 302; in Fig. 3A related in Figs. 1-2, 4-22) connected to word lines and bit lines (within Fig. 6F related in Figs. 1-5, 7-22) and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation (see fore example in Figs. 7A-7C related in Figs. 1-6, 8-22); and a control circuit connected to the word lines and the bit lines (within Fig. 3A related in Figs. 1-2, 4-22) and configured to: use, during a setup clock of a loop of a plurality of loops of a program-verify operation (see for example in Figs. 16A-16C, 17A, 17B, 20 related in Figs. 1-15, 18-19, 21-22), a first verify voltage ramping time period of a plurality of verify voltage ramping time periods based on a data state being verified during the loop (see for example in Figs. 16A-16C, 17A, 17B, 20 related in Figs. 1-15, 18-19, 21-22); and use, during a setup clock of another loop of a plurality of loops of a program-verify operation, a second verify voltage ramping time period of the plurality of verify voltage ramping time periods based on a data state being verified during the other loop (see for example in Figs. 16A-16C, 17A, 17B, 20 related in Figs. 1-15, 18-19, 21-22).
For apparatus claims 1-7, MPEP 2112.01(I) instructs examiners, “When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed inherent.” Zainuddin et al. disclose a substantially identical memory apparatus; the recited functions are presumed inherent. See also, MPEP Foreword (“[T]he Manual contains instructions to examiners, as well as other material in the nature of information and interpretation, and outlines the current procedures which the examiners are required or authorized to follow in appropriate cases in the normal examination of a patent application.”).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicants are reminded that argument of counsel is not evidence (see MPEP 2145(I)). Applicants are reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 2, Zainuddin, for example in Figs. 1-22, discloses wherein each verify voltage ramping time period of the plurality of verify voltage ramping time periods corresponds to a set of data states of the plurality of data states (see for example in Figs. 16A-16C, 17A, 17B, 20 related in Figs. 1-15, 18-19, 21-22, as discussed above).
Regarding claim 3, Zainuddin, for example in Figs. 1-22, discloses wherein the first verify voltage ramping time period is for a different duration than the second verify voltage ramping time period (see for example in Figs. 16A-16C, 17A, 17B, 20 related in Figs. 1-15, 18-19, 21-22, as discussed above).
Regarding claim 4, Zainuddin, for example in Figs. 1-22, discloses wherein the first verify voltage ramping time period corresponds to a first set of data states of the plurality of data states and the second verify voltage ramping time period corresponds to a second set of data states of the plurality of data states (see for example in Figs. 16A-16C, 17A, 17B, 20 related in Figs. 1-15, 18-19, 21-22, as discussed above).
Regarding claim 5, Zainuddin, for example in Figs. 1-22, discloses wherein each data state of the first set of data states is different from each data state in the second set of data states (see for example in Figs. 16A-16C, 17A, 17B, 20 related in Figs. 1-15, 18-19, 21-22, as discussed above).
Regarding claim 6, Zainuddin, for example in Figs. 1-22, discloses wherein each data state of the first set of data states is of a lower data state than each data state in the second set of data states (see for example in Figs. 16A-16C, 17A, 17B, 20 related in Figs. 1-15, 18-19, 21-22, as discussed above).
Regarding claim 7, Zainuddin, for example in Figs. 1-22, discloses wherein a duration of the first verify voltage ramping time period is longer than a duration of the second verify voltage ramping time period (see for example in Figs. 16A-16C, 17A, 17B, 20 related in Figs. 1-15, 18-19, 21-22, as discussed above).
Regarding Independent Claim 8, Zainuddin, for example in Figs. 1-22, discloses a method of operating (see for example in Figs. 12, 21 related in Figs. 1-11, 13-20, 22) a non-volatile semiconductor memory device (e.g., 300; in Fig. 3A related in Figs. 1-2, 4-22), the method comprising: using, during a setup clock of a loop of a plurality of loops of a program-verify operation (implied the steps of 870-884; in Fig. 8 related in Figs. 1-7, 9-22), a first verify voltage ramping time period of a plurality of verify voltage ramping time periods (implied the step of 2105-2109; in Fig. 21 related in Figs. 1-20, 22) based on a data state of a plurality of data states (implied the steps of 960-972; in Fig. 12 related in Figs. 1-11, 13-22) being verified during the loop (implied the steps of 884; in Fig. 8 related in Figs. 1-7, 9-22); and using, during a setup clock of another loop of a plurality of loops of a program-verify operation (implied the steps of 870-884; in Fig. 8 related in Figs. 1-7, 9-22), a second verify voltage ramping time period of the plurality of verify voltage ramping time periods based on a data state the plurality of data states (implied the steps of 960-972; in Fig. 12 related in Figs. 1-11, 13-22) being verified during the other loop (implied the steps of 884; in Fig. 8 related in Figs. 1-7, 9-22).
Regarding claim 9, Zainuddin, for example in Figs. 1-22, discloses wherein each verify voltage ramping time period of the plurality of verify voltage ramping time periods corresponds to a set of data states of the plurality of data states (implied the steps of 960-972; in Fig. 12 related in Figs. 1-11, 13-22, as discussed above).
Regarding claim 10, Zainuddin, for example in Figs. 1-22, discloses wherein the first verify voltage ramping time period is for a different duration than the second verify voltage ramping time period (implied the step of 2105-2109; in Fig. 21 related in Figs. 1-20, 22, as discussed above).
Regarding claim 11, Zainuddin, for example in Figs. 1-22, discloses wherein the first verify voltage ramping time period corresponds to a first set of data states of the plurality of data states and the second verify voltage ramping time period corresponds to a second set of data states of the plurality of data states (implied the steps of 960-972; in Fig. 12 related in Figs. 1-11, 13-22, as discussed above).
Regarding claim 12, Zainuddin, for example in Figs. 1-22, discloses wherein each data state of the first set of data states is different from each data state in the second set of data states (implied the steps of 960-972; in Fig. 12 related in Figs. 1-11, 13-22, as discussed above).
Regarding claim 13, Zainuddin, for example in Figs. 1-22, discloses wherein each data state of the first set of data states is of a lower data state than each data state in the second set of data states (implied the steps of 960-972; in Fig. 12 related in Figs. 1-11, 13-22, as discussed above).
Regarding claim 14, Zainuddin, for example in Figs. 1-22, discloses wherein a duration of the first verify voltage ramping time period is longer than a duration of the second verify voltage ramping time period (implied the step of 2105-2109; in Fig. 21 related in Figs. 1-20, 22, as discussed above).
Regarding Independent Claim 15, Zainuddin, for example in Figs. 1-22, discloses an apparatus (see for example in Figs. 1A, 3A related in Figs. 2, 4-22 and under 35 U.S.C 112(f)), comprising: a means for using, during a setup clock of a loop of a plurality of loops of a program-verify operation (implied the steps of 870-884; in Fig. 8 related in Figs. 1-7, 9-22), a first verify voltage ramping time period of a plurality of verify voltage ramping time periods (implied the step of 2105-2109; in Fig. 21 related in Figs. 1-20, 22) based on a data state of a plurality of data states (implied the steps of 960-972; in Fig. 12 related in Figs. 1-11, 13-22) being verified during the loop (implied the steps of 884; in Fig. 8 related in Figs. 1-7, 9-22); and a means for using, during a setup clock of another loop of a plurality of loops of a program-verify operation (implied the steps of 870-884; in Fig. 8 related in Figs. 1-7, 9-22), a second verify voltage ramping time period of the plurality of verify voltage ramping time periods (implied the step of 2105-2109; in Fig. 21 related in Figs. 1-20, 22) based on a data state of the plurality of data states being verified during the other loop (implied the steps of 884; in Fig. 8 related in Figs. 1-7, 9-22).
Regarding claim 16, Zainuddin, for example in Figs. 1-22, discloses wherein each verify voltage ramping time period of the plurality of verify voltage ramping time periods corresponds to a set of data states of the plurality of data states (implied the steps of 960-972; in Fig. 12 related in Figs. 1-11, 13-22, as discussed above).
Regarding claim 17, Zainuddin, for example in Figs. 1-22, discloses wherein the first verify voltage ramping time period is for a different duration than the second verify voltage ramping time period (implied the step of 2105-2109; in Fig. 21 related in Figs. 1-20, 22, as discussed above).
Regarding claim 18, Zainuddin, for example in Figs. 1-22, discloses wherein the first verify voltage ramping time period corresponds to a first set of data states of the plurality of data states and the second verify voltage ramping time period corresponds to a second set of data states of the plurality of data states (implied the steps of 960-972; in Fig. 12 related in Figs. 1-11, 13-22, as discussed above).
Regarding claim 19, Zainuddin, for example in Figs. 1-22, discloses wherein each data state of the first set of data states is of a lower data state than each data state in the second set of data states (implied the steps of 960-972; in Fig. 12 related in Figs. 1-11, 13-22, as discussed above).
Regarding claim 20, Zainuddin, for example in Figs. 1-22, discloses wherein a duration of the first verify voltage ramping time period is longer than a duration of the second verify voltage ramping time period (implied the step of 2105-2109; in Fig. 21 related in Figs. 1-20, 22, as discussed above).
Applicant are reminded that when presenting amendments to claims. In order to be fully responsive, an attempt should be made to point out the patentable novelty (see MPEP 714.04). Additionally, Applicant should point out where and/or how the originally filed disclosure supports the amendment(s) (see MPEP 2163 (II)(A)).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 11/28/2025