Prosecution Insights
Last updated: October 23, 2026
Application No. 18/740,858

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§112
Filed
Jun 12, 2024
Priority
Jun 15, 2023 — JP 2023-098769
Examiner
CHEN, DAVID Z
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
KIOXIA Corporation
OA Round
1 (Non-Final)
45%
Grant Probability
Moderate
1-2
OA Rounds
1y 2m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 45% of resolved cases
45%
Career Allowance Rate
313 granted / 695 resolved
-23.0% vs TC avg
Strong +50% interview lift
Without
With
+50.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
50 currently pending
Career history
762
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.0%
+9.0% vs TC avg
§102
24.8%
-15.2% vs TC avg
§112
25.3%
-14.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 695 resolved cases

Office Action

§102 §112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment/Restriction Applicant’s election without traverse of Species I, Embodiment 1: FIG. 7 (6a, 31), and Claims 1-3, 8-12, 17-18, and 20 in the reply filed on September 18, 2026 is acknowledged. Thus, Claims 4-7, 13-16, and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on September 18, 2026. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 18, the limitation “and including the conductive layer” fails to specify what “includes” the conductive layer. It is not clear whether the wire includes the conductive layer or the first insulator includes the conductive layer. Thus, the limitation renders the claim indefinite and clarification is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-2, 8-9, and 20 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2016/0172368 A1 to Pang et al. (“Pang”). As to claim 1, Pang discloses a semiconductor device comprising: a first insulator (857a); a conductive layer (849); and a film (836) provided between the first insulator (857a) and the conductive layer (849) and containing carbon (C) (¶ 0136) or silicon (Si) (See Fig. 8, ¶ 0136, ¶ 0146, ¶ 0154, ¶ 0158, ¶ 0160, ¶ 0161). As to claim 2, Pang discloses further comprising a first barrier metal film (848) provided between the film (836) and the conductive layer (849) (See Fig. 8, ¶ 0158). As to claim 8, Pang further discloses wherein the concentration of carbon between the first insulator (857a) and the conductive layer (849) is equal to or higher than a predetermined value (See ¶ 0136). As to claim 9, Pang further discloses wherein the predetermined value is 1×1019 atom/cm3 (See ¶ 0136). As to claim 20, Pang discloses a semiconductor device manufacturing method comprising: forming a first insulator (821); forming a film (836) containing carbon (C) (¶ 0136) or silicon (Si) above the first insulator (821); and forming a conductive layer (866) above the film (836) (See Fig. 8, ¶ 0136, ¶ 0146, ¶ 0150, ¶ 0154, ¶ 0158, ¶ 0160, ¶ 0161, ¶ 0162). Claim(s) 1-3, 10-12, 17-18, and 20 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2020/0144284 A1 to Choi et al. (“Choi”). As to claim 1, Choi discloses a semiconductor device comprising: a first insulator (193); a conductive layer (180); and a film (191) provided between the first insulator (193) and the conductive layer (180) and containing carbon (C) (¶ 0031) or silicon (Si) (See Fig. 1, ¶ 0024-¶ 0034). As to claim 2, Choi discloses further comprising a first barrier metal film (metal nitride) provided between the film (191) and the conductive layer (180) (See ¶ 0024). As to claim 3, Choi further discloses wherein the conductive layer (180) contains tungsten (W) (See ¶ 0024). As to claim 10, Choi discloses further comprising: a stacked body (132, 180) in which insulating layers (132) and the conductive layers (180) are alternately stacked in a first direction; a semiconductor layer (153) disposed in the first direction in the stacked body (132, 180); a second insulator (150 tunnel) disposed in the first direction between the stacked body (132, 180) and the semiconductor layer (153); a third insulator (150 electric) disposed in the first direction between the stacked body (132, 180) and the second insulator (150 tunnel); and a fourth insulator (150 blocking) disposed in the first direction between the stacked body (132, 180) and the third insulator (150 electric), wherein the first insulator (193) is disposed between the conductive layers (180) and the insulating layers (132) and between the conductive layers (180) and the fourth insulator (150 blocking) (See Fig. 1, ¶ 0027, ¶ 0029). As to claim 11, Choi discloses further comprising a first barrier metal film (metal nitride) provided between the film (191) and the conductive layer (180) (See ¶ 0024). As to claim 12, Choi further discloses wherein the conductive layer (180) contains tungsten (W) (See ¶ 0024). As to claim 17, Choi further discloses wherein the concentration of carbon between the first insulator (193) and the conductive layer (180) is equal to or higher than a predetermined value (See ¶ 0031) (Notes: the predetermined value to adjust diffusion). As to claim 18, Choi discloses further comprising a wire (197) disposed at the first insulator (193) and including the conductive layer (180) (See ¶ 0034) (Notes: the limitation “wire” is interpreted as a connector). As to claim 20, Choi discloses a semiconductor device manufacturing method comprising: forming a first insulator (157); forming a film (191) containing carbon (C) or silicon (Si) above the first insulator (157); and forming a conductive layer (197) above the film (191) (See Fig. 1, ¶ 0024-¶ 0034). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID CHEN/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Jun 12, 2024
Application Filed
Sep 30, 2026
Non-Final Rejection mailed — §102, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
45%
Grant Probability
95%
With Interview (+50.2%)
3y 7m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 695 resolved cases by this examiner. Grant probability derived from career allowance rate.

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