DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-11 and 20 in the reply filed on 8/17/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/8/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-11 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SUWA et al. US 11011443.
Re claim 1, SUWA teaches an apparatus (fig6C and 13), comprising:
a pair of substrates (top and bottom 27, fig13C, col8 line 49);
a conductive material (15, 12, fig6C, col 7 line 1-10) formed on portions of respective inwardly facing surfaces of insulative materials (26, fig13C, col8 line 15-20) of the pair of substrates (top and bottom 27, fig13C, col8 line 49);
a step (step in 15, fig6C) formed in or on the conductive material on one of the pair of substrates (15, fig6C);
a lead frame having leads (32, 33, 34, fig13, col10 line 10-15), portions of the leads mounted between the conductive materials (15, 12, fig6C and 13C, col 7 line 1-10) on the pair of substrates (top and bottom 27, fig13C, col8 line 49);
electronic components (left and right 11, fig6C, col7 line 10-15) having different respective thicknesses (fig6C, col7 line 10-15) mounted between the conductive materials (15, 12, fig6C, col 7 line 1-10) on the pair of substrates, one of the electronic components being thicker or thinner than one other of the electronic components (left 11 thicker than right 11, fig6C, col7 line 10-15) or the leads of the lead frame, or the leads being thicker or thinner than one of the electronic components;
the step (step in 15, fig6C) having a step thickness dimensioned to facilitate electrical contact between a thickest one of the electronic components (left 11, fig6C, col7 line 1-25) or the leads of the lead frame with the step formed in or on the conductive material (15, fig6C, col 7 line 1-10) on the one of the pair of substrates (top 27, fig13C, col8 line 49) and the conductive material (12, fig6C, col 7 line 1-10) on the one other of the pair of substrates (bottom 27, fig13C, col8 line 49); and
an electrical signal path (fig12, 13A and 13B) between the electronic components (left and right 11, fig6C, col7 line 10-15) having different respective thicknesses or the leads of the lead frame disposed in electrical contact with the step formed in or on the conductive material on the one of the pair of substrates and the conductive material on the one other of the pair of substrates.
Re claim 2, SUWA teaches the apparatus of claim 1, comprising a circuit pattern (fig6C, 13A-13C) formed of the conductive material (15, 12, fig6C, col 7 line 1-10) on one of the pair of substrates (top and bottom 27, fig13C, col8 line 49), the circuit pattern partially defining the electrical signal path between the electronic components (left and right 11, fig6C, col7 line 10-15) having different respective thicknesses or the leads of the lead frame (fig6C and 13A-13C).
Re claim 3, SUWA teaches the apparatus of claim 1, comprising an opening formed through one of the pair of substrates (space between 11, fig6C and 13C).
Re claim 4, SUWA teaches the apparatus of claim 3, comprising an insulative fill material (22, fig13C, col9 line1) which substantially occupies interstices between the electronic components (left and right 11, fig6C, col7 line 10-15) having different respective thicknesses and the portions of the leads (33, 34, fig13C, col10 line 10-15) of the lead frame mounted between the pair of substrates (top and bottom 27, fig13C, col8 line 49).
Re claim 5, SUWA teaches the apparatus of claim 4, wherein the insulative fill material (22, fig13C, col9 line1) substantially surrounds the electronic components (left and right 11, fig6C, col7 line 10-15) having different respective thicknesses and the portions of the leads (33, 34, fig13C, col10 line 10-15) of the lead frame mounted between the pair of substrates (top and bottom 27, fig13C, col8 line 49).
Re claim 6, SUWA teaches the apparatus of claim 1, wherein the lead frame comprises an extended input/output lead (32, 33, 34, fig13, col10 line 10-15) extending continuously between opposing sidewalls of the pair of substrates (sidewall of 27 above and below X-X in fig13B).
Re claim 7, SUWA teaches the apparatus of claim 1, wherein the electronic components (left and right 11, fig6C, col7 line 10-15) having different respective thicknesses comprise field-effect transistors (fig12 and 13A-13C) having different respective thicknesses and the electrical signal path is between a source of one field-effect transistor and a drain of a further field-effect transistor (fig12 and 13A-13C).
Re claim 8, SUWA teaches the apparatus of claim 1, wherein the electronic components having different respective thicknesses comprise metal-oxide-semiconductor field-effect transistors (left and right 11 as MOSFETs, fig6C, col9 line 55-60 ) having different respective thicknesses and the electrical signal path is between a source of one metal-oxide-semiconductor field-effect transistor and a drain of a further metal-oxide- semiconductor field-effect transistor (fig12 and 19A-B).
Re claim 9, SUWA teaches the apparatus of claim 1, further comprising bonding material (13, fig6C, col6 line 59) between one or more of the electronic components (left and right 11, fig6C, col7 line 10-15) having different respective thicknesses, the leads of the lead frame (32, 33, 34, fig13A-13C, col10 line 10-15), the step (step in 15, fig6C) formed in or on the conductive material of the one of the pair of substrates (top and bottom 27, fig13C, col8 line 49), or the conductive material of the one other of the pair of substrates, to facilitate electrical connectivity therebetween (fig13A-13B).
Re claim 10, SUWA teaches the apparatus of claim 9, wherein the bonding material (13, fig6C, col6 line 59) forms a portion of the electrical signal path (fig12 and 13A-13B).
Re claim 11, SUWA teaches the apparatus of claim 10, wherein the bonding material comprises back side metallization or solder (13, fig6C, col3 line 60-65).
Re claim 20, SUWA teaches an apparatus (fig6C and 13), comprising:
a first substrate (top 26, fig13C, col8 line 15-20) having a first insulative material (top 26, fig13C, col8 line 15-20) with a first inwardly facing surface and a first inner conductive material (15, fig6C, col 7 line 1-10) formed on a portion of the first inwardly facing surface;
a second substrate (bottom 26, fig13C, col8 line 15-20) having a second insulative material (bottom 26, fig13C, col8 line 15-20) with a second inwardly facing surface and a second inner conductive material (12, fig6C, col 7 line 1-10) formed on a portion of the second inwardly facing surface;
a lead frame having leads (32, 33, 34, fig13, col10 line 10-15) mounted between the first substrate and the second substrate (top and bottom 26, fig13C), the lead frame having an extended input/output lead (32, 33, 34, fig13, col10 line 10-15) extending continuously between opposing sidewalls (sidewall of 26 above and below X-X in fig13B) of the first substrate and the second substrate;
electronic components (left and right 11, fig6C, col7 line 10-15) having different respective thicknesses mounted between the first substrate and the second substrate;
a step (step in 15, fig6C) formed in or on the first inner conductive material overlying the portion of the first inwardly facing surface of the first substrate;
the step having a step thickness (step in 15, fig6C, col7 line 1-20) dimensioned to facilitate electrical contact between a thickest one of the electronic components (left 11, fig6C, col7 line 10-15) having different respective thicknesses or of the leads of the lead frame with the step formed in or on the first inner conductive material (15, fig6C, col 7 line 1-10) formed on the first substrate (top 26, fig13C, col8 line 15-20) and the second inner conductive material (12, fig6C, col 7 line 1-10) formed on the second substrate (bottom 26, fig13C, col8 line 15-20); and
a heat dissipating outer conductive material (top and bottom 27, fig13C, col8 line 49) formed on a portion of an outwardly facing surface of the first insulative material of the first substrate or the second insulative material of the second substrate (top and bottom 26, fig13C, col8 line 15-20).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOMING LIU whose telephone number is (571)270-0384. The examiner can normally be reached Monday-Friday, 9am-8pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XIAOMING LIU/Examiner, Art Unit 2812
Prosecution Insights