DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-16 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (JP2023-112068 Japan 07/07/2023).
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 06/12/2024, 01/28/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “N bytes in which the word line is selected,…a second voltage higher than the first voltage…2xN bytes…a third voltage higher than the first voltage…” as recited in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 1-4, 9-12, 15-16’s “sequencer” that is “configured to” perform recited operations;
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9-16 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Takekida (US 12,068,053 B2).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 9, Takekida, for example in Figs. 1-17, discloses a memory device (e.g., 1; in Fig. 1 related in Figs. 2-17) comprising:
a CMOS layer (e.g., layer 200; in Figs. 12-13 related in Figs. 1-11, 14-17), a first memory layer (e.g., 10A/10B; in Figs. 12-13 related in Figs. 1-11, 14-17), and a second memory layer stacked in a first direction (e.g., 10A/10B; in Figs. 12-13 related in Figs. 1-11, 14-17); and
sequencer (e.g., 13; in Fig. 1 related in Figs. 2-17), wherein
the first memory layer includes a plurality of first bit lines (e.g., BL; in Fig. 3 related in Figs. 1-2, 4-17) and a plurality of first strings (within BLK; in Figs. 1, 6-7 related in Figs. 2-5, 8-17), and one end of each of the first strings is coupled to each of the first bit lines (via sense amplifier SAU; in Fig. 4 related in Figs. 1-3, 5-17),
the second memory layer includes a plurality of second bit lines and a plurality of second strings (see for example in Figs. 3, 6-7, 12-13 related in Figs. 1-2, 4-5, 8-11, 14-17), and one end of each of the second strings is coupled to each of the second bit lines (see for example in Figs. 3, 6-7, 12-13 related in Figs. 1-2, 4-5, 8-11, 14-17),
the CMOS layer includes a plurality of sense amplifier units configured to be able to determine data (e.g., SAU; in Fig. 3 related in Figs. 1-2, 4-17), the sense amplifier units are respectively coupled to the first bit lines and are respectively coupled to the second bit lines (see for example in Figs. 3-4, 6-7, 12-13 related in Figs. 1-2, 5, 8-11, 14-17), each of the sense amplifier units includes a first transistor coupled to any of the first bit lines, a second transistor coupled to any of the second bit lines (within SAU; in Figs. 3-4, 6-7, 12-13 related in Figs. 1-2, 5, 8-11, 14-17), and a sense node coupled to each of the first transistor and the second transistor (e.g., ND1/ND2; in Fig. 4 related in Figs. 1-3, 5-17), and the sense amplifier units includes a plurality of first sense amplifier units and a plurality of second sense amplifier units (see for example in Fig. 3 related in Figs. 1-2, 4-17),
in the read operation, the sequencer is configured to:
apply a voltage of a first logic level to the first transistor of each of the first sense amplifier units (e.g., transistor 24 is turn on/off; in Figs. 3-4 related in Figs. 1-2, 5-17), and apply a voltage of a second logic level different from the first logic level to the second transistor of each of the first sense amplifier units (e.g., transistor 24 is turn off/on; in Figs. 3-4 related in Figs. 1-2, 5-17), and apply a voltage of the second logic level to the first transistor of each of the second sense amplifier units (e.g., transistor 24 is turn on/off; in Figs. 3-4 related in Figs. 1-2, 5-17), and apply a voltage of the first logic level to the second transistor of each of the second sense amplifier units (e.g., transistor 24 is turn on/off; in Figs. 3-4 related in Figs. 1-2, 5-17). The structure in of the prior art (Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 10, Takekida, for example in Figs. 1-17, discloses wherein the sequencer is further configured to: in the first read operation, control to turn on each of the first transistor of the first sense amplifier unit and the second transistor of the second sense amplifier unit (see for example in Figs. 3-4 related in Figs. 1-2, 5-17, as discussed above), and control to turn off each of the second transistor of the first sense amplifier unit and the first transistor of the second sense amplifier unit (see for example in Figs. 3-4 related in Figs. 1-2, 5-17, as discussed above), and in the second read operation, control to turn on each of the second transistor of the first sense amplifier unit and the first transistor of the second sense amplifier unit (see for example in Figs. 3-4 related in Figs. 1-2, 5-17, as discussed above), and control to turn off each of the first transistor of the first sense amplifier unit and the second transistor of the second sense amplifier unit (see for example in Figs. 3-4 related in Figs. 1-2, 5-17, as discussed above). Also, the structure in of the prior art (Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 11, Takekida, for example in Figs. 1-17,discloses wherein each of the first strings includes a first memory cell (within memory array; in Figs. 1-2, 6-7, 11-13 related in Figs. 3-5, 8-10, 14-17), a third transistor, and a fourth transistor coupled in series (e.g., SGD/SGS; in Figs. 2, 11-13 related in Figs. 1, 3-10, 14-17), the first memory layer further includes a first wiring, a second wiring, and a first word line (see for example in Figs. 11-13 related in Figs. 1-10, 14-17), the first wiring is coupled to the third transistor of each of the first strings (see for example in Figs. 11-13 related in Figs. 1-10, 14-17), the second wiring is coupled to the fourth transistor of each of the first strings (see for example in Figs. 11-13 related in Figs. 1-10, 14-17), and the first word line is coupled to the first memory cell of each of the first strings (see for example in Figs. 11-13 related in Figs. 1-10, 14-17), each of the second strings includes a second memory cell (see for example in Figs. 11-13 related in Figs. 1-10, 14-17), a fifth transistor, and a sixth transistor coupled in series, the second memory layer further includes a third wiring, a fourth wiring, and a second word line, the third wiring is coupled to the fifth transistor of each of the second strings (see for example in Figs. 11-13 related in Figs. 1-10, 14-17), the fourth wiring is coupled to the sixth transistor of each of the second strings, and the second word line is coupled to the second memory cell of each of the second strings and is electrically coupled to the first word line (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above), and the sequencer is further configured to in a first read operation in which the first and second word lines are selected (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above), apply a first voltage to the first wiring, apply a second voltage higher than the first voltage to the second wiring, apply the first voltage to the third wiring, and apply the second voltage to the fourth wiring (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above). Also, the structure in of the prior art (Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 12, Takekida, for example in Figs.1-17, discloses wherein the sequencer is further configured to in a second read operation in which the first and second word lines are selected (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above), apply the second voltage to the first wiring, apply the first voltage to the second wiring, apply the second voltage to the third wiring, and apply the first voltage to the fourth wiring (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above). Also, the structure in of the prior art (Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 13, Takekida, for example in Figs. 1-17, discloses wherein in an even first string coupled to an even first bit line among the first strings, a threshold voltage of the third transistor is lower than a threshold voltage of the fourth transistor (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above), in an odd first string coupled to an odd first bit line among the first strings, a threshold voltage of the third transistor is higher than a threshold voltage of the fourth transistor (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above), in an even second string coupled to an even second bit line among the second strings, a threshold voltage of the fifth transistor is higher than a threshold voltage of the sixth transistor (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above), and in an odd second string coupled to an odd second bit line among the second strings, a threshold voltage of the fifth transistor is lower than a threshold voltage of the sixth transistor (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above). Also, the structure in of the prior art (Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 14, Takekida, for example in Figs. 1-17, discloses wherein the first voltage is between a threshold voltage of the third transistor and a threshold voltage of the fourth transistor in the even first string, between a threshold voltage of the third transistor and a threshold voltage of the fourth transistor in the first odd string (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above), between a threshold voltage of the fifth transistor and a threshold voltage of the sixth transistor in the second even string, and between a threshold voltage of the fifth transistor and a threshold voltage of the sixth transistor in the second odd string (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above), and the second voltage is higher than a threshold voltage of the fourth transistor in the even first string, higher than a threshold voltage of the third transistor in the odd first string (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above), higher than a threshold voltage of the fifth transistor in the even second string, and higher than a threshold voltage of the sixth transistor in the odd second string (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above). Also, the structure in of the prior art (Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 15, Takekida, for example in Figs. 1-17, discloses wherein each of the sense amplifier units includes a seventh transistor coupled to any of the first bit lines (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above), an eighth transistor coupled to any of the second bit lines (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above), and a first node coupled to each of the seventh transistor and the eighth transistor, and in the read operation, the sequencer is configured to apply a voltage of the second logic level to each of the seventh transistor and the eighth transistor of each of the sense amplifier units (see for example in Figs. 11-13 related in Figs. 1-10, 14-17, as discussed above). Also, the structure in of the prior art (Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 16, Takekida, for example in Figs. 1-17, discloses wherein each of the sense amplifier units includes a seventh transistor coupled to any of the first bit lines (see for example in Figs. 1, 3-4 related in Figs. 2, 5-17, as discussed above), an eighth transistor coupled to any of the second bit lines, and a first node coupled to each of the seventh transistor and the eighth transistor (see for example in Figs. 1, 3-4 related in Figs. 2, 5-17, as discussed above), and in the read operation, the sequencer is configured to apply a voltage of the first logic level to each of the seventh transistor and the eighth transistor of each of the sense amplifier units, and apply a third voltage to the first node (see for example in Figs. 1, 3-4 related in Figs. 2, 5-17, as discussed above). Also, the structure in of the prior art (Takekida) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Maejima et al (US 11,264,106 B2 hereinafter “Maejima_1”) in view of Maejima (US 2020/0091175 A1 hereinafter “Maejima_2”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Maejima_1, for example in Figs. 1-67, discloses a memory device (e.g., memory device 1; in Fig. 1 related in Figs. 2-67) comprising:
a plurality of bit lines (e.g., BL0-BLm; in Fig. 2 related in Figs. 1, 3-67);
a plurality of strings each having one end coupled to the bit lines (e.g., NSa; in Fig. 2 related in Figs. 1, 3-67), each of the strings including a memory cell (e.g., MTs; in Fig. 2 related in Figs. 1, 3-67), a first transistor (e.g., DT0/STa; in Fig. 2 related in Figs. 1, 34-14), and a second transistor coupled in series (e.g., STa/DT0; in Fig. 2 related in Figs. 1, 3-67);
a first wiring coupled to the first transistor of each of the strings (e.g., SGDL0/SGSaL; in Fig. 2 related in Figs. 1, 3-67);
a second wiring coupled to the second transistor of each of the strings (e.g., SGSaL/SGDL0; in Fig. 2 related in Figs. 1, 3-67);
a word line coupled to the memory cell of each of the strings (e.g., WLa; in Fig. 2 related in Figs. 1, 3-67); and
a sequencer (e.g., 13; in Fig. 1 related in Figs. 2-67), wherein
the sequencer is configured to: in read operation, apply a first voltage to one of the first wiring line and the second wiring line (e.g., Vsg; in Figs. 60-61 related in Figs. 1-59, 62-67), and apply a second voltage higher than the first voltage to the other of the first wiring line and the second wiring line (e.g., VB1/VC0; in Figs. 60-61 related in Figs. 1-59, 62-67). Maejima discloses that the data of each page is determined by reads.
However, Maejima_1 is silent with regard to the sequencer is configured to: in a read operation of N (N is an integer equal to or larger than 1) bytes; and in a read operation of 2×N bytes in which the word line is selected, apply a third voltage higher than the first voltage to each of the first wiring and the second wiring.
In the same field of endeavor, Maejima_2, for example in Figs. 1-25, discloses the sequencer is configured to: in a read operation of N (N is an integer equal to or larger than 1) bytes (e.g., in the bundle mode can hold data of N bytes; see paragraph [0115]); and in a read operation of 2×N bytes in which the word line is selected (e.g., in the normal mode can hold the data 2N bytes; see paragraph [0115]), apply a third voltage higher than the first voltage to each of the first wiring and the second wiring (e.g., the sequencer is configured to change or adjust SGD and SGS voltage for read/write operation; in Figs. 14, 20-21 related in Figs. 1-13, 15-19, 22-25).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Maejima_1 such as semiconductor memory device including memory cells at opposing sides of semiconductor (see for example in Figs. 1-67 of Maejima_1) by incorporating the teaching of Maejima_2 such as memory system and semiconductor memory device (see for example in Figs. 1-25 of Maejima_2), for the purpose of controlling the controller sends an instruction to the device to execute the operation in the first mode or the second mode (Maejima_2, see abstract).
The structure in of the prior art (Maejima_1 and Maejima_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding clam 2, the above Maejima_1/Maejima_2, combination discloses further comprising: sense amplifier units (e.g., SAU; in Fig. 8 related in Figs. 1-7, 9-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above) respectively coupled to the bit lines (e.g., BL; in Fig. 8 related in Figs. 1-7, 9-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above), the sense amplifier units being configured to be able to determine data, wherein each of the sense amplifier units includes a third transistor coupled to any of the bit lines (see for example in Fig. 9 related in Figs. 1-8, 10-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above), and the sequencer is further configured to: in a read operation of N bytes in which the word line is selected, control to turn on the third transistors of the number included in the sense amplifier units and corresponding to N bytes, and control to turn off the remaining third transistors (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above); and in a read operation of 2×N bytes in which the word line is selected, control to turn on the third transistors of the number included in the sense amplifier units and corresponding to 2×N bytes (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above). Also, the structure in of the prior art (Maejima_1 and Maejima_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 3, the above Maejima_1/Maejima_2, combination discloses wherein the read operation of N bytes has first and second modes (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above), and the sequencer is further configured to in the first mode, apply the first voltage and the second voltage to the first wiring and the second wiring, respectively (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above), and in the second mode, apply the second voltage and the first voltage to the first wiring and the second wiring, respectively (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above). Also, the structure in of the prior art (Maejima_1 and Maejima_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 4, the above Maejima_1/Maejima_2, combination discloses wherein in the read operation of N bytes, the sequencer is further configured to: in the case of the first mode, control to turn on the third transistor coupled to an even bit line included in the bit lines (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above), and in the case of the second mode, control to turn on the third transistor coupled to an odd bit line included in the bit lines (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above). Also, the structure in of the prior art (Maejima_1 and Maejima_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 5, the above Maejima_1/Maejima_2, combination discloses 5. The memory device of claim 3, wherein in an even string coupled to the even bit line among the strings, a threshold voltage of the first transistor is lower than a threshold voltage of the second transistor (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above), and in an odd string coupled to the odd bit line among the strings, a threshold voltage of the first transistor is higher than a threshold voltage of the second transistor (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above). Also, the structure in of the prior art (Maejima_1 and Maejima_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 6, the above Maejima_1/Maejima_2, combination discloses wherein the first voltage is between a threshold voltage of the first transistor and a threshold voltage of the second transistor in the even string (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above), and between a threshold voltage of the first transistor and a threshold voltage of the second transistor in the odd string (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above), and the second voltage is higher than a threshold voltage of the second transistor in the even string and higher than a threshold voltage of the first transistor in the odd string (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above). Also, the structure in of the prior art (Maejima_1 and Maejima_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 7, the above Maejima_1/Maejima_2, combination discloses further comprising: a substrate, wherein in each of the strings, the first transistor, the second transistor, and the memory cell are arranged in a direction intersecting a surface of the substrate (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above). Also, the structure in of the prior art (Maejima_1 and Maejima_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 8, the above Maejima_1/Maejima_2, combination discloses wherein the second voltage is substantially equal to the third voltage (see for example in Figs. 1-67 of Maejima_1 and also see in Figs. 1-25 of Maejima_2, as discussed above). Also, the structure in of the prior art (Maejima_1 and Maejima_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 12/09/2025