DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 16 July 2026 has been entered.
Amendment
Acknowledgment is made of applicant’s Amendment, filed 16 July 2026. The changes and remarks disclosed therein have been considered.
No Claims have been cancelled or added by the Amendment. Therefore, claims 1-16 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (JP2023-112068 07/07/2023 Japan).
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 1-4’s “sequencer” that is “configured to” perform recited operations;
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Shibata et al (US 11,688,458 B2 hereinafter “Shibata”) in view of Maejima (US 2020/0091175 A1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Shibata, for example in Figs. 1-84, discloses a memory device (e.g., memory device 10; in Fig. 1 related in Figs. 2-84) comprising:
a plurality of bit lines (e.g., BL0-BLm; in Fig. 78 related in Figs. 1-77, 79-84);
a plurality of strings (e.g., strings NS; in Fig. 78 related in Figs. 1-77, 79-84) including a first string (e.g., string NS; in Fig. 78 related in Figs. 1-77, 79-84) and a second string (e.g., string NS; in Fig. 78 related in Figs. 1-77, 79-84) each having one end coupled to the bit lines (see for example in Fig. 78 related in Figs. 1-77, 79-84), each of the strings including a select transistor connected to one of the bit lines (e.g., SGD0A; in Fig. 78 related in Figs. 1-77, 79-84), a memory cell (e.g., MTs are connected to WL; in Fig. 78 related in Figs. 1-77, 79-84), a first transistor (e.g., SGD1A; in Fig. 78 related in Figs. 1-77, 79-84), and a second transistor coupled in series (e.g., SGD2A; in Fig. 78 related in Figs. 1-77, 79-84);
a first wiring coupled to the first transistor of each of the strings (e.g., wiring connected to SGD1A; in Fig. 78 related in Figs. 1-77, 79-84);
a second wiring coupled to the second transistor of each of the strings (e.g., SGD2A; in Fig. 78 related in Figs. 1-77, 79-84);
a third wiring coupled to the select transistor of each of the strings (e.g., SGD0A; in Fig. 78 related in Figs. 1-77, 79-84);
a word line coupled to the memory cell of each of the strings (e.g., WL0-WL7; in Fig. 78 related in Figs. 1-77, 79-84); and
a sequencer (e.g., 14; in Fig. 1 related in Figs. 2-84), wherein
the sequencer is configured to:
in read operation, apply a first voltage to one of the first wiring and the second wiring (see for example in Figs. 78-79 related in Figs. 1-77, 80-84), apply a second voltage higher than the first voltage to the other of the first wiring and the second wiring (see for example in Figs. 78-79 related in Figs. 1-77, 80-84), and apply a turn on voltage to the third wiring (see for example in Figs. 78-79 related in Figs. 1-77, 80-84), and apply turn on voltage to the third wiring (see for example in Figs. 78-79 related in Figs. 1-77, 80-84),
wherein, in each of the strings (e.g., NAND string NS; in Fig. 78 related in Figs. 1-77, 79-84), the first transistor (e.g., SGD1A; in Fig. 78 related in Figs. 1-77, 79-84) and the second transistor (e.g., SGD2A; in Fig. 78 related in Figs. 1-77, 79-84) are disposed between the select transistor (e.g., SGD0A; in Fig. 78 related in Figs. 1-77, 79-84) and the memory cell (e.g., memory cell transistor MT; in Fig. 78 related in Figs. 1-77, 79-84),
wherein, in each of the strings (e.g., NAND string NS; in Fig. 78 related in Figs. 1-77, 79-84), the first transistor (e.g., SGD1A; in Fig. 78 related in Figs. 1-77, 79-84) is disposed between the select transistor (e.g., SGD0A; in Fig. 78 related in Figs. 1-77, 79-84) and the second transistor (e.g., SGD2A; in Fig. 78 related in Figs. 1-77, 79-84), and the second transistor (e.g., SGD2A; in Fig. 78 related in Figs. 1-77, 79-84) is disposed between the first transistor (e.g., SGD1A; in Fig. 78 related in Figs. 1-77, 79-84) and the memory cell (e.g., memory cell transistor MT; in Fig. 78 related in Figs. 1-77, 79-84),
wherein the first transistor of the first string and the second transistor of the second string have a first threshold voltage (see for example in Figs. 78-79 related in Figs. 1-77, 80-84), the second transistor of the first string and the first transistor of the second string have a second threshold voltage different from the first threshold voltage (see for example in Figs. 78-79 related in Figs. 1-77, 80-84). Shibata discloses that the data of each page is determined by reads.
However, Shibata is silent with regard to the sequencer is configured to: in a read operation of N (N is an integer equal to or larger than 1) bytes; and in a read operation of 2×N bytes in which the word line is selected, apply a third voltage higher than the first voltage to each of the first wiring and the second wiring,
In the same field of endeavor, Maejima, for example in Figs. 1-25, discloses the sequencer is configured to: in a read operation of N (N is an integer equal to or larger than 1) bytes (e.g., in the bundle mode can hold data of N bytes; see paragraph [0115]); and in a read operation of 2×N bytes in which the word line is selected (e.g., in the normal mode can hold the data 2N bytes; see paragraph [0115]), apply a third voltage higher than the first voltage to each of the first wiring and the second wiring (e.g., the sequencer is configured to change or adjust SGD and SGS voltage for read/write operation; in Figs. 14, 20-21 related in Figs. 1-13, 15-19, 22-25).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Shibata such as semiconductor memory device and memory system at opposing sides of semiconductor (see for example in Figs. 1-84 of Shibata) by incorporating the teaching of Maejima such as memory system and semiconductor memory device (see for example in Figs. 1-25 of Maejima), for the purpose of controlling the controller sends an instruction to the device to execute the operation in the first mode or the second mode (Maejima, see abstract).
The structure in of the prior art (Shibata and Maejima) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
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Regarding clam 2, the above Shibata/Maejima, combination discloses further comprising: sense amplifier units (e.g., SAU(0)-SAU(m-1); in Fig. 2 related in Figs. 1, 3-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above) respectively coupled to the bit lines (e.g., BL0-BL(m-1); in Fig. 2 related in Figs. 1, 3-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above), the sense amplifier units being configured to be able to determine data, wherein each of the sense amplifier units includes a third transistor coupled to any of the bit lines (see for example in Fig. 78 related in Figs. 1-77, 79-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above), and the sequencer is further configured to: in a read operation of N bytes in which the word line is selected, control to turn on the third transistors of the number included in the sense amplifier units and corresponding to N bytes, and control to turn off the remaining third transistors (see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above); and in a read operation of 2×N bytes in which the word line is selected, control to turn on the third transistors of the number included in the sense amplifier units and corresponding to 2×N bytes (s see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above). Also, the structure in of the prior art (Shibata and Maejima) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 3, the above Shibata/Maejima, combination discloses wherein the read operation of N bytes has first and second modes (see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above), and the sequencer is further configured to in the first mode, apply the first voltage and the second voltage to the first wiring and the second wiring, respectively (see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above), and in the second mode, apply the second voltage and the first voltage to the first wiring and the second wiring, respectively (see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above). Also, the structure in of the prior art (Shibata and Maejima) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 4, the above Shibata/Maejima, combination discloses wherein in the read operation of N bytes, the sequencer is further configured to: in the case of the first mode, control to turn on the third transistor coupled to an even bit line included in the bit lines (see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above), and in the case of the second mode, control to turn on the third transistor coupled to an odd bit line included in the bit lines (see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above). Also, the structure in of the prior art (Shibata and Maejima) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 5, the above Shibata/Maejima, combination discloses 5. The memory device of claim 3, wherein in the first string coupled to an even bit line among the strings, a threshold voltage of the first transistor is lower than a threshold voltage of the second transistor (see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above), and in the second string coupled to an odd bit line among the strings, a threshold voltage of the first transistor is higher than a threshold voltage of the second transistor (see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above). Also, the structure in of the prior art (Shibata and Maejima) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 6, the above Shibata/Maejima, combination discloses wherein the first voltage is between a threshold voltage of the first transistor and a threshold voltage of the second transistor in the first string (see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above), and between a threshold voltage of the first transistor and a threshold voltage of the second transistor in the second string (see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above), and the second voltage is higher than a threshold voltage of the second transistor in the first string and higher than a threshold voltage of the first transistor in the second string (see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above). Also, the structure in of the prior art (Shibata and Maejima) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 7, the above Shibata/Maejima, combination discloses further comprising: a substrate, wherein in each of the strings, the first transistor, the second transistor, and the memory cell are arranged in a direction intersecting a surface of the substrate (see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above). Also, the structure in of the prior art (Shibata and Maejima) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 8, the above Shibata/Maejima, combination discloses wherein the second voltage is substantially equal to the third voltage (see for example in Figs. 78-79 related in Figs. 1-77, 80-84 of Shibata and also see in Figs. 1-25 of Maejima, as discussed above). Also, the structure in of the prior art (Shibata and Maejima) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Allowable Subject Matter
Claims 9-16 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations.
Response to Arguments
Applicant's arguments filed 16 July 2026 have been fully considered but they are not persuasive.
Applicant argues that the Figs. 78-79 of Shibata does not discloses the specific configuration recited in amended independent claim 1 of first and second transistors of first and second strings and their respective thresholds.
In response the Figs. 78-79 of Shibata and in view of Maejima discloses substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 07/25/2026
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