Prosecution Insights
Last updated: July 17, 2026
Application No. 18/741,020

PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF

Non-Final OA §102
Filed
Jun 12, 2024
Priority
Sep 14, 2023 — CN 202311183893.3
Examiner
JANG, BO BIN
Art Unit
Tech Center
Assignee
Kore Semiconductor Co. Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
541 granted / 613 resolved
+28.3% vs TC avg
Moderate +8% lift
Without
With
+7.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
24 currently pending
Career history
629
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
82.0%
+42.0% vs TC avg
§102
10.9%
-29.1% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 613 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant's claim for foreign priority based on an application CN 202311183893.3 filed in the China National Intellectual Property Administration (CNIPA) on September 4, 2023 and receipt of a certified copy thereof. Claim Objections Claims 1-3 and 6-8 are objected to because of the following informalities: In claim 1, line 9, “each of the plurality of first electrode pads” should read --a corresponding one of the plurality of first electrode pads--. In claim 2, line 2, “a wall surface of each of the plurality of positioning holes” should read --a wall surface of a corresponding one of the plurality of positioning holes--. In claim 3, lines 2-3, “a conductive pillar used to bond to each of the plurality of second electrode pads” should read --a conductive pillar bonded to a corresponding one of the plurality of second electrode pads--. In claim 6, line 13, “each of the plurality of first electrode pads” should read --a corresponding one of the plurality of first electrode pads--. In claim 7, line 2, “a wall surface of each of the plurality of positioning holes” should read --a wall surface of a corresponding one of the plurality of positioning holes--. In claim 8, line 2, “a conductive pillar used to bond to each of the plurality of second electrode pads” should read --a conductive pillar bonded to a corresponding one of the plurality of second electrode pads--. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3-6 and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai TW I776678 B1 (the original document and a machine-generated English translation thereof are used in rejection). Regarding claim 1, Lai teaches a package structure (e.g., 2, Fig. 1E; translation [7]-[49]), comprising: a first electronic element (e.g., 20, Fig. 1E) having a plurality of first electrode pads (e.g., 200, Fig. 1E); a positioning layer (e.g., 21, Fig. 1E; translation [19], [41]) formed on the first electronic element and having a plurality of positioning holes (e.g., 210, Fig. 1E) exposing the plurality of first electrode pads; and a second electronic element (e.g., 22, Fig. 1E) disposed on the positioning layer and having a plurality of second electrode pads (e.g., 220, Fig. 1E), wherein the plurality of second electrode pads are provided with a plurality of conductive bumps (e.g., 25, Fig. 1E; translation [28]) accommodated in the plurality of positioning holes, so that each of the plurality of conductive bumps is in contact with each of the plurality of first electrode pads (e.g., Fig. 1E), such that the second electronic element is electrically connected to the first electronic element via the plurality of conductive bumps (e.g., Fig. 1E). Regarding claim 3, Lai teaches the package structure of claim 1, wherein each of the plurality of conductive bumps includes a conductive pillar (e.g., 231, Fig. 1E; translation [24]) used to bond to each of the plurality of second electrode pads and a conductive bonding material (e.g., 232, Fig. 1E; translation [25]) formed on the conductive pillar. Regarding claim 4, Lai teaches the package structure of claim 3, wherein the conductive bonding material is a solder material (e.g., translation [25]). Regarding claim 5, Lai teaches the package structure of claim 1, wherein a material for forming the positioning layer is an organic insulating material (e.g., translation [41]). Regarding claim 6, Lai teaches a method of fabricating a package structure (e.g., Figs. 1A-1E; translation [7]-[49]), comprising: providing a first electronic element (e.g., 20, Fig. 1A) having a plurality of first electrode pads (e.g., 200, Fig. 1A) and a second electronic element (e.g., 22, Figs. 1B-1C) having a plurality of second electrode pads (e.g., 220, Figs. 1B-1C); forming a positioning layer (e.g., 21, Fig. 1A) on the first electronic element, and forming a plurality of conductive bumps (e.g., 25, Figs. 1B-1C) on the plurality of second electrode pads of the second electronic element, wherein the positioning layer has a plurality of positioning holes (e.g., 210, Fig. 1A) exposing the plurality of first electrode pads; inserting the plurality of conductive bumps into the plurality of positioning holes, so that the second electronic element is bonded onto the positioning layer (e.g., Fig. 1D; translation [45], [46]), wherein the plurality of conductive bumps are free from being in contact with the plurality of first electrode pads in the plurality of positioning holes (e.g., Fig. 1D; the conductive bumps 25 do not contact the first electrode pads 200 in the holes 210); and heating the plurality of conductive bumps (e.g., Fig. 1E; translation [46], [47]), so that each of the plurality of conductive bumps is in contact with each of the plurality of first electrode pads (e.g., Fig. 1E), wherein the second electronic element is electrically connected to the first electronic element via the plurality of conductive bumps (e.g., Fig. 1E). Regarding claim 8, Lai teaches the method of claim 6, wherein each of the plurality of conductive bumps includes a conductive pillar (e.g., 231, Figs. 1B-1C; translation [24]) used to bond to each of the plurality of second electrode pads and a conductive bonding material (e.g., 232, Figs. 1B-1C; translation [25]) formed on the conductive pillar. Regarding claim 9, Lai teaches the method of claim 8, wherein the conductive bonding material is a solder material (e.g., translation [25]). Regarding claim 10, Lai teaches the method of claim 6, wherein a material for forming the positioning layer is an organic insulating material (e.g., translation [41]). Allowable Subject Matter Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if amended to overcome the claim objection stated above. Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if amended to overcome the claim objection stated above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) OR 571-272-1000. /BO B JANG/Primary Examiner, Art Unit 2818 June 12, 2026
Read full office action

Prosecution Timeline

Jun 12, 2024
Application Filed
Jun 16, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
96%
With Interview (+7.6%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 613 resolved cases by this examiner. Grant probability derived from career allowance rate.

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