DETAILED ACTION
This action is responsive to the application filed June 12, 2024. Claims 1-8 are pending. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on June 12, 2024. This IDS has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. It is noted that the current title denotes two independent inventions. Additionally, the term “IC Chip” as a descriptor is referenced in an improper dependent claim (see 112(d) rejection below). Applicant may correct the deficiency by removing the term from the title.
The following title is suggested: Complimentary Memory Circuit.
Claim Rejections - 35 USC § 112 – Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claim 1 recites the phrases “a (first/second) terminal which is connectable to”, and “voltage can be applied”. As apparent from the claim language, the respective terminal would only perform the recited function if it transmits a signal to the gates of the targeted transistor; however, the terminal is not required to be connected to the target transistor because it only has to be connectable. In other words, the functionality recited may never happen because the terminal may never be connected to the transistor thereby never transmitting the signal.
Similarly, the respective terminal would only perform the recited function if the specified voltage is actually applied to the terminal; however the voltage is not required to be applied because it can or may be applied. In other words, the specified voltage may never be applied to the terminal and in fact, the terminal may be left completely unconnected and floating.
For these reasons, the claim is indefinite. See In re Collier, 397 F.2d 1003, 1006 (CCPA 1968). Dependent claims 2-8 do not resolve the above indefiniteness. For purposes of compact prosecution, claim 1 will be treated with respect to prior art as if the respective terminals “is connected to” the gates of the targeted transistors and that the power-supply voltage “is applied”.
Claim Rejections - 35 USC § 112 – Improper Dependent Form
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 8 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
A dependent claim must "specify a further limitation of the subject matter claimed" by the preceding claim. The phrase "comprising the memory circuit according to claim 1" merely incorporates all the limitations of claim 1 (which describes a memory circuit) into a broader item (an IC chip) without adding a new, specific limitation or feature to that IC chip beyond simply containing the circuit.
A proper dependent claim must narrow the scope of the claim from which it depends. This claim, by introducing the broader concept of an "IC chip" as the main apparatus (potentially an independent statutory class of invention), might be interpreted as an independent claim in dependent form, but it fails to limit the IC chip in a new way, other than by reference.
Claim 1 is for a "memory circuit," which is an apparatus claim. Claim 8 is for an "IC chip," which is also an apparatus. While the claim classes are the same, the structure of the claim makes it a "claim in dependent form that is effectively an independent claim" because it describes a new item (the chip) that merely contains the old item (the circuit).
Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chindalore et al. (US 20050007820; “Chindalore”) in view of Roehr et al. (US 20210272610 “Roehr”).
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Regarding independent claim 1, notwithstanding the indefiniteness rejection for claim 1 above, Chindalore discloses a memory circuit that is provided to an IC chip, the memory circuit comprising:
which includes a reference transistor (Fig. 4. which illustrates reference transistor 46 within the reference circuit 42);
a first terminal which is connectable to a gate of the first memory transistor and a gate of the second memory transistor (Fig. 5 which illustrates in detail memory array 32 and specifically the gates of memory cells 50 and 56 which are connected to signal Vcell which originates from a terminal on the voltage control circuit 48 of Fig. 4. It is noted that the instant application actually indicates (in para. 24) "Specifically, the switch 52 is turned OFF while the switch 51 has been turned ON, and the switch 52 is turned ON while the switch 51 has been turned OFF" indicating that there are other components (switches) between the terminal and the memory cell(s) as is the same in Chindalore),
and to which a first power-supply voltage can be applied (Fig. 4. which illustrates a voltage 49 from the voltage control circuit 48 being applied);
a second terminal which is connectable to a gate of the reference transistor (Fig. 4. which illustrates a terminal Vref connected to the gate of the reference transistor 46),
and to which a second power-supply voltage can be applied (Fig. 4. which illustrates a voltage 49 from the voltage control circuit 48 being applied);
and a detection unit which detects a magnitude relationship between current that flows through the first memory cell or the second memory cell (Fig. 4 where it illustrates the sense amplifier 40),
and current that flows through the reference cell (Fig. 4 where it illustrates the current iREF going to the sense amplifier 40).
Chindalore is silent with respect to the memory cells being complementary and to the detail of the reference cell.
However, Roehr teaches a complementary cell which includes (para. 12; " complementary data items are written to the two memory cells. For example, if a logical “1” is written to the first memory cell, a logical “0” is written to the second memory cell, and vice versa")
a first memory cell that includes a first memory transistor (Fig. 2D: cell 116_1),
and a second memory cell that includes a second memory transistor (Fig. 2D: cell 116_2);
a reference cell (para. 33; "In another case, not shown, only one of the stored data values, thus the value of the first memory cell 116_1 or the value of the second memory cell 116_2, would be compared with a reference value to provide the digital output signal on the output line 122". The embodiment for a reference value supplied to the sense amplifier is illustrated in Fig. 1B:120)
Chindalore and Roehr are from the same field of endeavor as applicant’s invention directed to memory circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chindalore’s current reference and switching mechanisms with the teachings of Roehr’s complementary memory cells to form a non-volatile redundant memory array. Doing so would ensure high reliability of the data and long term data retention.
Regarding claim 2, Chindalore and Roehr combined disclose the limitations of claim 1.
As applied, Chindalore further discloses wherein the first power-supply voltage and the second power-supply voltage is a same power-supply voltage (Fig. 4 where it illustrates the voltages VREF and VCELL which are necessarily matched to track each other. See also para. 20; "A threshold voltage of a read reference cell tracks the program/erase threshold voltage of the normal memory cells").
Regarding claim 3, Chindalore and Roehr combined disclose the limitations of claim 2.
As applied, Chindalore further discloses wherein the first terminal and the second terminal are independent terminals (Fig. 4 where it illustrates terminals VREF and VCELL as unique).
Regarding claim 4, Chindalore and Roehr combined disclose the limitations of claim 1.
As applied, Chindalore further discloses wherein the reference cell includes a reference selection transistor which is connected to the reference transistor (Fig. 4 voltage control circuit 48 which is connected to the reference transistor 46. It is noted that as Chindalore's circuits are digital, the VREF output of the voltage control circuit is necessarily coupled to a transistor which must be turned on (selected) to output voltage).
Regarding claim 5, Chindalore and Roehr combined disclose the limitations of claim 1.
As applied, Chindalore further discloses further comprising first switches which are arranged between the gate of the first memory transistor and the gate of the second memory transistor and the first terminal (Fig. 4 where it illustrates transistor 52. See also para. 23; "FIG. 4 illustrates the read control circuit 41 of the memory of FIG. 3 in more detail". Therefore, it is noted that transistor 52 is an example of part of row decoder circuit 36 of Fig. 3 which necessarily switches between terminal 49 and the various memory transistors in array 32).
Regarding claim 6, Chindalore and Roehr combined disclose the limitations of claim 1.
As applied, Chindalore further discloses further comprising a second switch which is arranged between the gate of the reference transistor and the second terminal (Fig. 4 voltage control circuit 48 which is connected to the gate of the reference transistor 46. It is noted that as Chindalore's circuits are digital, the VREF output of the voltage control circuit is necessarily coupled to a transistor (switch) )
Regarding claim 7, Chindalore and Roehr combined disclose the limitations of claim 1.
As applied, Chindalore further discloses further comprising:
a third switch having a first end which is connected to a first bit line to be connected to the first memory cell; and a fourth switch having a first end which is connected to a second bit line to be connected to the second memory cell, wherein a second end of the third switch and a second end of the fourth switch are connected commonly to an input end of the detection unit (Fig. 4 where it illustrates transistor 54 which is part of column decoder 34 of Fig. 3 and which is connected on one side to the bitline of memory cell 50 and on the other side to sense amplifier 40. See also para. 21; "Memory 32 is an array of programmable non-volatile memory cells coupled to bit lines and word lines and is shown in more detail in FIG. 5", " column decoder 34 select one or more of the memory cells to be accessed").
Regarding claim 8, notwithstanding the rejection for improper dependent form above, Chindalore and Roehr combined disclose the limitations of claim 1.
As applied, Chindalore further discloses an IC chip, comprising the memory circuit according to Claim 1 (para. 30; "FIG. 6-FIG. 11 illustrate, in cross-sectional views, a method for making the nanocrystal memory array 32 and the reference cell 46 in an integrated circuit 62 in accordance with the present invention")
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Or-Bach et al. (US 20210313345) - complimentary memory cells & using a current reference for single ended sense amp.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825