DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 9, and 16-20 are rejected for indefiniteness.
Regarding claim 9, the claim recites, "an angle relative to the substrate," however, this element has already been identified in claim 8. Claim 9 is improper antecedent basis because it is unclear if this is the same angle from claim 8 or a new angle. To further prosecution, Examiner will assume the former. Proper correction is required.
Regarding claims 6 and 16, the claims recite, "a second portion" for both the first and second interconnect. The element is indefinite because it is unclear if these are the same second portions or different ones. To further prosecution, Examiner will assume the latter. Proper correction is required.
Regarding claim 17, the claim recites, "a first portion" and "a second portion" for both the first and second metal-containing routing layers. These elements are indefinite because it is unclear if these are the same first portions and second portions or different ones. To further prosecution, Examiner will assume the latter. Proper correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5, and 7-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Motoyama (US 20240178127 A1).
Regarding claim 1, Motoyama teaches a semiconductor structure (300, Fig 3) comprising:
a substrate (500, Fig 5; starting substrate, [0038]);
a first interconnect (301, Fig 3);
an insulator material (601, Fig 6; shown as base dielectric in Fig 3);
a second interconnect (303) separated (shown separated) from the first interconnect (301) by the insulator material (601);
a tilted super via (305) connecting (shown connecting) the first interconnect (301) to the second interconnect (303); and
a third interconnect (302) disposed between (shown between) the first interconnect (301) and the second interconnect (303), wherein the tilted super via (305) bypasses (shown bypassing) the third interconnect (302).
Regarding claim 2, Motoyama teaches the structure of claim 1 and goes on to teach wherein the first interconnect (301, Fig 3) and the second interconnect (303) are vertically separated (shown vertically separated) by the insulator material (601).
Regarding claim 5, Motoyama teaches the structure of claim 1 and goes on to teach wherein the first interconnect (301, Fig 3) is parallel (shown parallel) to the second interconnect (303).
Regarding claim 7, Motoyama teaches the structure of claim 1 and goes on to teach wherein the first interconnect (301, Fig 3) and the second interconnect (303) are connected without an intermediate layer (shown connected without an intermediate layer).
Regarding claims 8 and 9, Motoyama teaches the structure of claim 1 and goes on to teach wherein the tilted super via (305, Fig 3) is characterized by an angle (A1: angle between sidewall of 305 in direct contact with base dielectric 601 to top surface of 302 which is parallel to the substrate) relative to the substrate (500) of less than or about 90°, and greater than 60° (shown less than 90° and greater than 60°).
Regarding claim 10, Motoyama teaches the structure of claim 1 and goes on to teach wherein the insulator material (601, Fig 6) comprises a silicon-containing material (SiN, [0035]).
Regarding claim 11, Motoyama teaches a semiconductor processing method (400, Fig 4) comprising:
forming a semiconductor structure (300, Fig 3) comprising:
a substrate (500, Fig 5; starting substrate, [0038]);
a first interconnect (301);
an insulator material (601, Fig 6; shown as base dielectric in Fig 3); and
a second interconnect (303) separated (shown separated) from the first interconnect (301) by the insulator material (601);
etching (408, patterning, Fig 4; wet or dry etch, [0034]) a non-orthogonal feature (1302, Fig 14) into the semiconductor structure (300); and
forming a tilted super via (305, Fig 3) in the non-orthogonal feature (1302) that connects (shown connecting) the first interconnect (301) to the second interconnect (303).
Regarding claim 12, Motoyama teaches the method of claim 11 and goes on to teach wherein the first interconnect (301, Fig 3) is parallel (shown parallel) to the second interconnect (303).
Regarding claim 13, Motoyama teaches the method of claim 11 and goes on to teach wherein the first interconnect (301, Fig 3) and the second interconnect (303) are connected without an intermediate layer (shown connected without intermediate layer).
Regarding claim 14, Motoyama teaches the method of claim 11 and goes on to teach wherein the semiconductor structure (300, Fig 3) further comprises a third interconnect (302) disposed between (shown between) the first interconnect (301) and the second interconnect (303), wherein the tilted super via (305) bypasses (shown bypassing) the third interconnect (302).
Regarding claim 15, Motoyama teaches the method of claim 11 and goes on to teach wherein the tilted super via (305, Fig 3) is characterized by an angle (A1: angle between sidewall of 305 in direct contact with base dielectric 601 to top surface of 302 which is parallel to the substrate) relative to the substrate (500) of between about 60° and about 89° (shown less than 89° and greater than 60°).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4, 6, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Motoyama (US 20240178127 A1) as applied to claims 1-2, 5, and 7-15 above, and further in view of Strong (US 20230197620 A1).
Regarding claim 3, Motoyama teaches the structure of claim 1, the first interconnect (301, Fig 3), the second interconnect (303), and the insulator material (601).
Motoyama fails to explicitly teach the first interconnect and the second interconnect are horizontally separated by the insulator material.
However, Strong teaches wherein the first interconnect and the second interconnect are horizontally separated (shown horizontally separated, Fig 2) by the insulator material.
Motoyama and Strong are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor structure devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Motoyama with the features of Strong to create a structure wherein the first interconnect and the second interconnect are horizontally separated by the insulator material because channels/vias that are angled/tilted, non-straight narrowed, non-straight shaped, etc. allow for using the channels/vias in different applications, and variations in the channel/via and/or plane size, shape, orientation, etc. as disclosed herein also enable the creation of testing sockets, simple fanout packages, etc. (Strong, [0023]).
Regarding claim 4, Motoyama teaches the structure of claim 1 and goes on to teach wherein the first interconnect (301, Fig 3) and the second interconnect (303) are routing layers (wiring levels, [0028]).
Motoyama fails to explicitly teach the first interconnect and the second interconnect are routing layers characterized by different pitches.
However, Strong teaches wherein the first interconnect and the second interconnect are routing layers characterized by different pitches (shown characterizing different pitches, Fig 2).
Motoyama and Strong are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor structure devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Motoyama with the features of Strong to create a structure wherein the first interconnect and the second interconnect are routing layers characterized by different pitches because channels/vias that are angled/tilted, non-straight narrowed, non-straight shaped, etc. allow for using the channels/vias in different applications, and variations in the channel/via and/or plane size, shape, orientation, etc. as disclosed herein also enable the creation of testing sockets, simple fanout packages, etc. (Strong, [0023]).
Regarding claim 6, Motoyama teaches the structure of claim 1, the first interconnect (301, Fig 3), the second interconnect (303), and the tilted super via (305).
Motoyama fails to explicitly teach a second tilted super via connecting a second portion of the first interconnect to a second portion of the second interconnect, wherein the tilted super via and the second tilted super via are nonparallel.
However, section 2144.04 of the MPEP, Subsection VI, states the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. Paragraph [0009] of the instant application discusses the inclusion of a second tilted super via, but is silent as to the criticality of the second titled super via to the design of the semiconductor structure. It would have been obvious to one of ordinary skill in the art before the time of filing to duplicate the first tilted super via to form a second titled super via in order to connect different portions of the first and second interconnects. Due to the sloped angle of the sidewalls of the super via, once duplicated, the tilted super via and the second tilted super via would be nonparallel.
Therefore, claim 6 is rejected in view of the obviousness of duplication of parts.
Also, while Motoyama fails to explicitly teach a second tilted super via connecting a second portion of the first interconnect to a second portion of the second interconnect, wherein the tilted super via and the second tilted super via are nonparallel, Strong teaches a second tilted super via (214B: second titled via, Fig 2) connecting (shown connecting) a second portion (226B: second portion of first interconnect) of the first interconnect to a second portion (224B: second portion of the second interconnect) of the second interconnect, wherein the tilted super via and the second tilted super via (214B) are nonparallel (shown nonparallel).
Motoyama and Strong are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor structure devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Motoyama with the features of Strong to create a structure wherein a second tilted super via connecting a second portion of the first interconnect to a second portion of the second interconnect, wherein the tilted super via and the second tilted super via are nonparallel because channels/vias that are angled/tilted, non-straight narrowed, non-straight shaped, etc. allow for using the channels/vias in different applications, and variations in the channel/via and/or plane size, shape, orientation, etc. as disclosed herein also enable the creation of testing sockets, simple fanout packages, etc. (Strong, [0023]).
Regarding claim 16, Motoyama teaches the method of claim 11, the semiconductor structure (300, Fig 3), the non-orthogonal feature (1302, Fig 14), the first interconnect (301, Fig 3), and the second interconnect (303).
Motoyama fails to explicitly teach etching a second non-orthogonal feature into the semiconductor structure, wherein the second non-orthogonal feature is unparallel with the non-orthogonal feature; and forming a second tilted super via in the non-orthogonal feature that connects a second portion of the first interconnect to a second portion of the second interconnect.
However, section 2144.04 of the MPEP, Subsection VI, states the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. Paragraph [0009] of the instant application discusses the inclusion of a second tilted super via, but is silent as to the criticality of the second titled super via to the design of the semiconductor structure. It would have been obvious to one of ordinary skill in the art before the time of filing to duplicate the first tilted super via to form a second titled super via in order to connect different portions of the first and second interconnects. Due to the sloped angle of the sidewalls of the super via, once duplicated, the tilted super via and the second tilted super via would be nonparallel.
Therefore, claim 16 is rejected in view of the obviousness of duplication of parts.
Also, while Motoyama fails to explicitly teach etching a second non-orthogonal feature into the semiconductor structure, wherein the second non-orthogonal feature is unparallel with the non-orthogonal feature; and forming a second tilted super via in the non-orthogonal feature that connects a second portion of the first interconnect to a second portion of the second interconnect, Strong teaches etching a second non-orthogonal feature (320, Fig 3) into the semiconductor structure, wherein the second non-orthogonal feature (320) is unparallel (shown unparallel) with the non-orthogonal feature; and
forming a second tilted super via (214B: second titled via, Fig 2) in the non-orthogonal feature that connects (shown connecting) a second portion (226B: second portion of first interconnect) of the first interconnect to a second portion (224B: second portion of the second interconnect) of the second interconnect.
Motoyama and Strong are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor structure devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Motoyama with the features of Strong to create a method further comprising: etching a second non-orthogonal feature into the semiconductor structure, wherein the second non-orthogonal feature is unparallel with the non-orthogonal feature; and forming a second tilted super via in the non-orthogonal feature that connects a second portion of the first interconnect to a second portion of the second interconnect because channels/vias that are angled/tilted, non-straight narrowed, non-straight shaped, etc. allow for using the channels/vias in different applications, and variations in the channel/via and/or plane size, shape, orientation, etc. as disclosed herein also enable the creation of testing sockets, simple fanout packages, etc. (Strong, [0023]).
Regarding claim 17, Motoyama teaches a semiconductor structure (300, Fig 3) comprising:
a substrate (500, Fig 5; starting substrate, [0038]);
a first metal-containing routing layer (301, Fig 3);
an insulator material (601, Fig 6; shown as base dielectric in Fig 3);
a second metal-containing routing layer (303) parallel (shown parallel) to the first metal-containing routing layer (301) and vertically separated (shown vertically separated) from the first metal-containing routing layer (301) by the insulator material (601);
a first tilted super via (305) connecting (shown connecting) a first portion (301A: portion of 301 directly connected to 305) of the first metal-containing routing layer (301) to a first portion (303A: portion of 303 directly connected to 305) of the second metal-containing routing layer (303).
Motoyama fails to explicitly teach a second tilted super via connecting a second portion of the first metal-containing routing layer to a second portion of the second metal-containing routing layer, wherein the first tilted super via and the second tilted super via are unparallel.
However, section 2144.04 of the MPEP, Subsection VI, states the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. Paragraph [0009] of the instant application discusses the inclusion of a second tilted super via, but is silent as to the criticality of the second titled super via to the design of the semiconductor structure. It would have been obvious to one of ordinary skill in the art before the time of filing to duplicate the first tilted super via to form a second titled super via in order to connect different portions of the first and second routing layers. Due to the sloped angle of the sidewalls of the super via, once duplicated, the tilted super via and the second tilted super via would be nonparallel.
Therefore, claim 17 is rejected in view of the obviousness of duplication of parts.
Also, while Motoyama fails to explicitly teach a second tilted super via connecting a second portion of the first metal-containing routing layer to a second portion of the second metal-containing routing layer, wherein the first tilted super via and the second tilted super via are unparallel, Strong teaches a second tilted super via (214B: second titled via, Fig 2) connecting (shown connecting) a second portion (226B: second portion of first routing layer) of the first metal-containing routing layer to a second portion (224B: second portion of the second routing layer) of the second metal-containing routing layer, wherein the first tilted super via and the second tilted super via (214B) are unparallel (shown unparallel).
Motoyama and Strong are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor structure devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Motoyama with the features of Strong to create a structure with a second tilted super via connecting a second portion of the first metal-containing routing layer to a second portion of the second metal-containing routing layer, wherein the first tilted super via and the second tilted super via are unparallel because channels/vias that are angled/tilted, non-straight narrowed, non-straight shaped, etc. allow for using the channels/vias in different applications, and variations in the channel/via and/or plane size, shape, orientation, etc. as disclosed herein also enable the creation of testing sockets, simple fanout packages, etc. (Strong, [0023]).
Regarding claim 18, the combination of Motoyama and Strong discloses the structure of claim 17. Strong teaches the second tilted super via (214B, Fig 2).
Motoyama goes on to teach wherein the first tilted super via (305, Fig 3) and the second tilted super via bypass (shown bypassing) a third metal-containing routing layer (302) disposed between (shown between) the first metal-containing routing layer (301) and the second metal-containing routing layer (303).
Regarding claim 19, the combination of Motoyama and Strong discloses the structure of claim 17. Motoyama goes on to teach wherein the first metal-containing routing layer (301, Fig 3) and the second metal-containing routing layer (303) are connected without an intermediate routing layer (shown connected without an intermediate layer).
Regarding claim 20, the combination of Motoyama and Strong discloses the structure of claim 17. Strong teaches the second tilted super via (214B, Fig 2).
Motoyama goes on to teach wherein the first tilted super via (305, Fig 3) and the second tilted super via are characterized by an angle (A1: angle between sidewall of 305 in direct contact with base dielectric 601 to top surface of 302 which is parallel to the substrate) relative to the substrate (500, Fig 5) of between about 60° and about 89° (shown less than 89° and greater than 60°).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Briggs (US 20180114752 A1) - skip vias
Herrault (US 10600739 B1) - angled vias connecting 2 different pitches
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights