Prosecution Insights
Last updated: August 16, 2026
Application No. 18/741,388

WIRING SUBSTRATE AND MANUFACTURING METHOD OF WIRING SUBSTRATE

Non-Final OA §103§112
Filed
Jun 12, 2024
Priority
Jun 14, 2023 — JP 2023-098046
Examiner
EGOAVIL, GUILLERMO J
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Toppan Holdings Inc.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
593 granted / 660 resolved
+21.8% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
18 currently pending
Career history
676
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
47.6%
+7.6% vs TC avg
§102
28.6%
-11.4% vs TC avg
§112
19.6%
-20.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 660 resolved cases

Office Action

§103 §112
DETAILED ACTION This Office Action is in response to an application that was filed on 06/12/2024. Claims 1-20 are presented for examination consideration. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings Objections The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s): The limitation phrase “second face” in the limitation “wherein a third face of the first electrode that faces a second face of the dielectric layer includes a contact portion that is in contact with the second face of the dielectric layer, and a non-contact portion that is not in contact with the second face of the dielectric layer” claimed in independent claim 1 must be shown, as detailed in the 112(b) rejection of claim 1. The limitation phrase “second face” in the limitation “wherein an outer circumference of the second face of the dielectric layer has a rectangular shape” claimed in claim 3 must be shown, as detailed in the 112(b) rejection of claim 3. The limitation phrase “second face” in the limitation “wherein the third face of the first electrode is greater in size than the second face of the dielectric layer” claimed in claim 10 must be shown, as detailed in the 112(b) rejection of claim 10. The limitation phrase “second face” in the limitation “wherein a fourth face of the dielectric layer facing the second face is greater in size than a fifth face of the second electrode facing the fourth face of the dielectric layer” claimed in claim 11 must be shown, as detailed in the 112(b) rejection of claim 11. The limitation phrases “fourth face” and “fifth face” in the limitation “wherein a fourth face of the dielectric layer facing the second face is greater in size than a fifth face of the second electrode facing the fourth face of the dielectric layer” claimed in claim 11 must be shown, as detailed in the 112(b) rejection of claim 11. There is NO transitional drawing(s) showing the step of “forming a mask covering the second conductive layer and removing the second seed layer and the dielectric layer” to obtain the Species of Fig. 1 in independent method claim 13. Therefore, giving the credibility to an ENABLING ISSUE with the method of claim 13. There is NO transitional drawing(s) showing the step of “forming a mask covering the second conductive layer and removing the second seed layer” to obtain the Species of Fig. 20 in independent method claim 17. Therefore, giving the credibility to an ENABLING ISSUE with the method of claim 17. No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification Objections The disclosure is objected to because of the following informalities: The filed specification is NOT supporting independent claim 1, as detailed in the Drawing Objection. The filed specification is NOT supporting claim 3, as detailed in the Drawing Objection. The filed specification is NOT supporting claim 10, as detailed in the Drawing Objection. The filed specification is NOT supporting claim 11, as detailed in the Drawing Objection. Appropriate correction is required as well as no new matter should be entered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-12 and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent Claim 1 recites the limitation phrase “second face” in the limitation “wherein a third face of the first electrode that faces a second face of the dielectric layer includes a contact portion that is in contact with the second face of the dielectric layer, and a non-contact portion that is not in contact with the second face of the dielectric layer”, is confusing. Specifically, the cited limitation structure in the cited limitation is CONTRADICTING the STRUCTURES of Figs. 1-2 and ¶[0103] of the PgPub, since the “six face” and NOT the limitation phrase “second face” that meets the cited limitation. Therefore, the cited limitation phrase should be CONSISTENT with Fig. 2, since it is the “sixth face S6 of the dielectric layer 16 that is in contact with the contact portion CP of the third face S3, and the sixth face S6 of the dielectric layer 16 is not in contact with non-contact portion NP of the third face S3”. Therefore, the cited limitation will be examined as “wherein a third face of the first electrode that faces a sixth face of the dielectric layer includes a contact portion that is in contact with the sixth face of the dielectric layer, and a non-contact portion that is not in contact with the sixth face of the dielectric layer” so as to be aligned with Figs. 1-2. Claims 2-12 are rejected since base claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph. Claim 3 recites the limitation phrase “second face” in the limitation “wherein an outer circumference of the second face of the dielectric layer has a rectangular shape”, is confusing. Specifically, as was stated in the 112(b) rejection of independent claim 1, the limitation structure of the cited limitation phrase is CONTRADICTING the STRUCTURES of Figs. 1-2 and ¶[0103] of the PgPub. Therefore, the cited limitation will be examined as “wherein an outer circumference of the sixth face of the dielectric layer has a rectangular shape”. Claim 10 recites the limitation phrase “second face” in the limitation “wherein the third face of the first electrode is greater in size than the second face of the dielectric layer”, is confusing. Specifically, as was stated in the 112(b) rejection of independent claim 1, the limitation structure of the cited limitation phrase is CONTRADICTING the STRUCTURES of Figs. 1-2 and ¶[0103] of the PgPub. Therefore, the cited limitation will be examined as “wherein the third face of the first electrode is greater in size than the sixth face of the dielectric layer”. Claim 11 recites the limitation phrases “second face”, “fourth face”, and “fifth face” in the limitation “wherein a fourth face of the dielectric layer facing the second face is greater in size than a fifth face of the second electrode facing the fourth face of the dielectric layer”, is confusing. Specifically, as was stated in the 112(b) rejection of independent claim 1, the limitation structure of the limitation phrase “second face” is CONTRADICTING the STRUCTURES of Figs. 1-2 and ¶[0103] of the PgPub. In addition, the limitation phrases “fourth face” and “fifth face” is CONTRADICTING the STRUCTURES of Figs. 1-2. Therefore, the cited limitation will be examined as “wherein a fifth face of the dielectric layer facing the sixth face is greater in size than a seventh face of the second electrode facing the fifth face of the dielectric layer” so as to be aligned with Figs. 1-2. In method independent claim 17, the limitation phrase “mask” in the first limitation “forming a mask covering part of the dielectric layer and removing the dielectric layer”, and the limitation phrase “mask” in the second limitation “forming a mask covering the second conductive layer and removing the second seed layer” are confusing. Specifically, is “mask” in the cited second limitation referring to a new limitation structure OR the “mask”, as indicated in the cited first limitation. Therefore, one skilled in the arts would not know if “mask” is referring to the limitation structure in cited first OR second limitations in the method. Consequently, the cited limitation phrase is not properly defined by the claim and NOT understandable in the filed disclosure. Claims 18-20 are rejected since base claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 3, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US20160218172A1 and Hsieh hereinafter), in view of Pietambaram et al. (US20230197697Al and Pietambaram hereinafter). Regarding claim 1, Hsieh discloses a wiring substrate (item 126 of Fig. 1B and ¶[0018-0019] shows and indicates wiring substrate 126 {integrated chip 126}) comprising: a substrate including a first face (items 101, 102a of Fig. 1B and ¶[0013_0015 & 0019-0020] shows and indicates substrate 101 {semiconductor substrate 101} including first face 101-surface-102a {surface of semiconductor substrate 101 adjacent to the surface of dielectric layer 102a}); a capacitor including a first electrode provided above the first face of the substrate, a dielectric layer provided above the first electrode, and a second electrode provided above the dielectric layer (items 100, 106, 108, 110 of Fig. 1B and ¶[0013-0018 & 0020] shows and indicates capacitor 100 {MIM capacitor 100} including first electrode 106 {CBM electrode 106} provided above first face 101-surface-102a of substrate 101; where dielectric layer 108 {high-k dielectric layer 108} provided above first electrode 106; and where second electrode 110 {CTM electrode 110} provided above dielectric layer 108); and a first insulating layer covering the first face of the substrate and the capacitor (item 102c of Fig. 1B and ¶[0020] shows and indicates first insulating layer 102c {dielectric layer 102c} covering first face 101-surface-102a of substrate 101 and the capacitor), wherein a third face of the first electrode that faces a sixth face of the dielectric layer includes a contact portion that is in contact with the sixth face of the dielectric layer, and a non-contact portion that is not in contact with the sixth face of the dielectric layer (item 124 of Fig. 1B and ¶[0013-0018 & 0020] shows and indicates where third face 106-surface-108_124 {surface of CBM electrode 106 adjacent to the surface dielectric layer 108 and the end surface of CBM contact via 124} of first electrode 106 that faces sixth face 108-surface-106 {surface of high-k dielectric layer 108 adjacent to the surface of CBM electrode 106} of dielectric layer 108 includes contact portion 106-contact-108 {contact between CBM electrode 106 and the high-k dielectric layer 108} that is in contact with sixth face 108-surface-106 of dielectric layer 108; and where non-contact portion 106-no-contact-124 {no contact of the high-k dielectric layer 108 at the point between CBM electrode 106 and CBM contact via 124} that is not in contact with sixth face 108-surface-106 of dielectric layer 108), and an outer circumference of the contact portion has a sawtooth shape (Fig. 1B and ¶[0015] shows and indicates the outer circumference of contact portion 106-contact-108 has a sawtooth shape {CBM electrode 106 has a zigzag shape to increases the surface area between the CBM electrode 106 and the CTM electrode 110}). Hsieh discloses the claimed invention except to disclose a glass substrate. Pietambaram discloses a glass substrate (items 104-1, 190 of Fig. 1A and ¶[0014 & 0020] indicates glass substrate 104-1 {glass substrate 104-1 integrated with MIM capacitor 190}; therefore, Hsieh will have the following limitations by incorporating the glass substrate of Pietambaram: a glass substrate including a first face; a capacitor including a first electrode provided above the first face of the glass substrate; and a first insulating layer covering the first face of the glass substrate and the capacitor). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a glass substrate into the structure of Hsieh. One would have been motivated in the wiring substrate of Hsieh and have the glass substrate, in order to reduce warpage and enable large Form Factor Devices, as indicated by Pietambaram in ¶[0014], in the wiring substrate of Hsieh. Regarding claim 3, modified Hsieh discloses a wiring substrate, wherein an outer circumference of the sixth face of the dielectric layer has a rectangular shape (Hsieh: Fig. 1B and ¶[0013-0018 & 0020] is extrapolated and understood to show where sixth face 108-surface-106 has a rectangular shape). Regarding claim 10, modified Hsieh discloses a wiring substrate, wherein the third face of the first electrode is greater in size than the sixth face of the dielectric layer (Hsieh: Fig. 1B and ¶[0013-0018 & 0020] shows where third face 106-surface-108_124 of first electrode 106 is greater in size than six face 108-surface-106 of dielectric layer 108). Regarding claim 11, modified Hsieh discloses a wiring substrate, wherein a fifth face of the dielectric layer facing the sixth face is greater in size than a seven face of the second electrode facing the fifth face of the dielectric layer (Hsieh: item 112 of Fig. 1B and ¶[0013-0018 & 0020-0022] shows where fifth face opposite-108-surface-106 {opposite surface of the surface of high-k dielectric layer 108 adjacent to the surface of CBM electrode 106} of dielectric layer 108 facing sixth face 108-surface-106 is greater in size than seven face 110-surface-112 {surface of CTM electrode 110 adjacent to the surface of CTM mask 112} of second electrode 110 facing fifth face opposite-108-surface-106 of dielectric layer 108). Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Pietambaram, as detailed in the rejection of claim 1 above, and in further view of Jones et al. (US 6740922 B2 and Jones hereinafter). Regarding claim 9, modified Hsieh discloses a wiring substrate, wherein the dielectric layer has a thickness of not less than 10 nm and not more than 5000 nm (Hsieh: Fig. 1B and ¶[0022] shows and indicates where dielectric layer 108 that is a high-k dielectric layer 108 has a thickness of not less than 10 nm and not more than 5000 nm {high-k dielectric layer 108 may have a thickness in a range of between about 10 Å [1 nm] and about 100 Å [10 nm]}). However, Hsieh and Pietambaram do not explicitly disclose wherein the dielectric layer is made of silicon nitride and has a thickness of not less than 10 nm and not more than 5000 nm. Jones discloses wherein the dielectric layer is made of silicon nitride and has a thickness of not less than 10 nm and not more than 5000 nm (items 510, 100 of Figs. 5-6 and 4:57-60 & 5:1-10 & 5:50-52 & 6:18-21 & claim 4 shows and indicates where dielectric layer 510 of capacitance of the device 100 employs high-K dielectrics that includes Silicon Nitride and has a thickness of not less than 10 nm and not more than 5000 nm {thickness of 100 nm}). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the dielectric layer is made of silicon nitride and has a thickness of not less than 10 nm and not more than 5000 nm into the structure of modified Hsieh. One would have been motivated in the wiring substrate of modified Hsieh and have the dielectric layer be made of silicon nitride and has a thickness of not less than 10 nm and not more than 5000 nm, in order to further increase the capacitance of the device by employing high-K dielectrics in the dielectric layer, as indicated by Jones in 6:18-21, and in order to further increase the capacitance of the device by having the dielectric layer be deposited to a thickness of 100 nm, as indicated by Jones in 4:57-60, in the wiring substrate of modified Hsieh. Allowable Subject Matter Method independent claim 13 and dependent claims 14-16 would be allowed if the claim 13 is rewritten or amended to overcome the Drawing Objections set forth in this Office Action. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GUILLERMO J EGOAVIL/Examiner, Art Unit 2847 /TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Jun 12, 2024
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
98%
With Interview (+8.3%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 660 resolved cases by this examiner. Grant probability derived from career allowance rate.

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