DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) submitted on June 12, 2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “an isolation film disposed in the second fin-type active region” (emphasis added), as recited in claims 8 and 19, must be shown or the feature(s) canceled from the claim(s). In addition, “a spacer structure covering a sidewall of the gate line and portions of the first source/drain region and the second source/drain region” (emphasis added), as recited in claim 10, and “a plurality of spacer structures covering the gate line, the first source/drain region and the second source/drain region” (emphasis added), as recited in claim 18, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1 and 10 are objected to because of the following informalities:
“second fin-type active region” should read “the second fin-type active region” (claim 1, lines 4 and 8 and claim 10, line 9);
“the first second device region” should read “the first device region” (claim 10, line 10).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5, 6, 9, 17 and 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In claim 5, lines 1-2, the limitation “a top surface of the first source/drain region in the first source/drain region” renders the claim indefinite because it is unclear how a top surface of the first source/drain region can be located in the first source/drain region. Examiner observes that independent claim 1 recites “a first source/drain region and a second source/drain region respectively in the first fin-type active region and second fin-type active region.” Therefore, it is suggested Applicant amend claim 5 to recite “a top surface of the first source/drain region in the first fin-type active region.” For examination purposes, the limitation in question will be interpreted as: a top surface of the first source/drain region in the first fin-type active region. Correction is respectfully requested.
In claim 5, line 3, the limitation “a top surface of the protective insulating film in the second source/drain region” renders the claim indefinite because it is unclear how a top surface of the protective insulating film can be located in the second source/drain region. Examiner observes that independent claim 1 recites “a protective insulating film disposed on the second source/drain region.” Therefore, it is suggested Applicant amend claim 5 to recite “a top surface of the protective insulating film on the second source/drain region.” For examination purposes, the limitation in question will be interpreted as: a top surface of the protective insulating film on the second source/drain region. Correction is respectfully requested.
In claim 5, lines 3-4, the limitation “a sidewall of the spacer structure in the first source/drain region and in the second source/drain region” renders the claim indefinite because it is unclear how a sidewall of the spacer structure can be located in the first source/drain region and in the second source/drain region. Examiner observes that independent claim 1 recites “a spacer structure disposed on the plurality of gate lines, the first source/drain region and the second source/drain region.” Therefore, it is suggested Applicant amend claim 5 to recite “a sidewall of the spacer structure on the first source/drain region and on the second source/drain region.” For examination purposes, the limitation in question will be interpreted as: a sidewall of the spacer structure on the first source/drain region and on the second source/drain region. Correction is respectfully requested.
Claim 6 is rejected because it depends from claim 5 and therefore inherits the indefiniteness of claim 5.
In claims 9, 17, and 20, the limitation “an n-channel metal-oxide semiconductor (NMOS) transistor is formed in the first source/drain region” renders the claims indefinite because it is unclear how the whole (i.e., a transistor) can be formed in a part thereof (i.e., a source/drain region). To overcome the rejection, it is suggested Applicant amend claims 9, 17 and 20 to recite “the first source/drain region is a part of an n-channel metal-oxide semiconductor (NMOS) transistor.” For examination purposes, the limitation in question will be interpreted as: the first source/drain region is a part of an n-channel metal-oxide semiconductor (NMOS) transistor. Correction is respectfully requested.
In claims 9, 17, and 20, the limitation “a p-channel MOS (PMOS) transistor is formed in the second source/drain region” renders the claims indefinite because it is unclear how the whole (i.e., a transistor) can be formed in a part thereof (i.e., a source/drain region). To overcome the rejection, it is suggested Applicant amend claims 9, 17 and 20 to recite “the second source/drain region is a part of a p-channel MOS (PMOS) transistor.” For examination purposes, the limitation in question will be interpreted as: the second source/drain region is a part of a p-channel MOS (PMOS) transistor. Correction is respectfully requested.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4 and 7-9, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0064390 A1 (hereinafter “Choi”) in view of US 2025/0022956 A1 (hereinafter “Li”).
Regarding claim 1, Choi discloses in Figs. 3A-3B, 4A-4D and related text an integrated circuit device (1; [0091]) comprising:
a first fin-type active region (120a; [0091]) and a second fin-type active region (120b; [0091]), each extending on a substrate (100; [0091]) in a first horizontal direction (X direction; [0095]);
a plurality of gate lines (131, 132; [0091]) on the first fin-type active region and the second fin-type active region, the plurality of gate lines extending in a second horizontal direction (Y direction; [0108]) that crosses the first horizontal direction;
a first source/drain region (12a; [0099]) and a second source/drain region (12b; [0099]) respectively in the first fin-type active region and the second fin-type active region, wherein each of the first source/drain region and the second source/drain region is disposed between the plurality of gate lines; and
a spacer structure (G1; [0113]) disposed on the plurality of gate lines, the first source/drain region and the second source/drain region.
Choi does not disclose a protective insulating film disposed on the second source/drain region and exposing the first source/drain region.
Li teaches in Figs. 1A, 1F, 1G and related text a protective insulating film (122; [0030]) disposed on the second source/drain region (108P; [0021]) and exposing the first source/drain region (108N; [0020]).
Choi and Li are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Choi with the specified features of Li because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a protective insulating film disposed on the second source/drain region and exposing the first source/drain region, as taught by Li, in order to increase longitudinal compressive stress in the channel region(s), thereby increasing the mobility of holes flowing in the channel region(s). Increasing the hole mobility in the channel region(s) of p-type field-effect transistors can improve the device performance (Li: [0016] and [0037]).
Regarding claim 2, Choi in view of Li disclose the integrated circuit device of claim 1.
Choi does not disclose the protective insulating film is formed on the second source/drain region to a thickness of about 1 nanometer (nm) to about 3 nm.
Li teaches in Figs. 1A, 1F, 1G and related text the protective insulating film (122; [0030]) is formed on the second source/drain region (108P; [0021]) to a thickness of about 1 nanometer (nm) to about 3 nm ([0032]).
Choi and Li are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Choi in view of Li with the specified features of Li because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the protective insulating film on the second source/drain region to a thickness of about 1 nanometer (nm) to about 3 nm, as taught by Li, in order to adequately provide the longitudinal compressive stress in the channel region(s) to enhance (increase) the mobility of holes in the channel region(s) for improving performance of a p-type field-effect transistor (Li: [0032]).
Regarding claim 4, Choi in view of Li disclose the integrated circuit device of claim 1.
Choi does not disclose the protective insulating film includes a silicon nitride film.
Li teaches the protective insulating film (122; [0030]) includes a silicon nitride film.
Choi and Li are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Choi in view of Li with the specified features of Li because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the protective insulating film to include a silicon nitride film, as taught by Li, in order to configure the protective insulating film to provide longitudinal compressive stress in the channel region(s) of p-type field effect transistors (Li: [0016], [0030] and [0037]).
Regarding claim 7, Choi in view of Li disclose the integrated circuit device of claim 1.
Choi does not disclose the protective insulating film is deposited on every facet of the second source/drain region.
Li teaches in Fig. 1A and related text the protective insulating film (122/122P; [0030]) is deposited on every facet of the second source/drain region (108P; [0021]).
Choi and Li are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Choi in view of Li with the specified features of Li because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the protective insulating film on every facet of the second source/drain region, as taught by Li, in order to increase longitudinal compressive stress in the channel region(s), thereby increasing the mobility of holes flowing in the channel region(s). Increasing the hole mobility in the channel region(s) of p-type field-effect transistors can improve the device performance (Li: [0016] and [0037]).
Regarding claim 8, Choi in view of Li disclose an isolation film (Choi: S; Fig. 4B; [0101]) disposed in the second fin-type active region, wherein a composition of the isolation film is different from a composition of the second source/drain region (the isolation film is an insulator, and the second source/drain region is a semiconductor).
Regarding claim 9, Choi in view of Li disclose the integrated circuit device of claim 1.
Choi does not disclose an n-channel metal-oxide semiconductor (NMOS) transistor is formed in the first source/drain region and a p-channel MOS (PMOS) transistor is formed in the second source/drain region.
Li teaches in Fig. 1A and related text an n-channel metal-oxide semiconductor (NMOS) transistor (102N; [0020]) is formed in the first source/drain region (108N; [0020]) and a p-channel MOS (PMOS) transistor (102P; [0021]) is formed in the second source/drain region (108P; [0021]).
Choi and Li are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Choi in view of Li with the specified features of Li because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form an n-channel metal-oxide semiconductor (NMOS) transistor in the first source/drain region and to form a p-channel MOS (PMOS) transistor in the second source/drain region, as taught by Li, in order to enable a complementary metal oxide semiconductor (CMOS) integrated circuit such as an inverter.
Claim(s) 10, 12, 13 and 15-17, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0238689 A1 (hereinafter “Yoon”) in view of Li.
Regarding claim 10, Yoon discloses in Figs. 1, 2A-2D and related text an integrated circuit device (100; [0027]) comprising:
a substrate (102; [0028]) including a first device region (RX1; [0028]), a second device region (RX2; [0028]), and a device isolation region (DTA; [0028]) defining the first device region and the second device region;
a first fin-type active region (F1; [0031]) in the first device region and a second fin-type active region (F2; [0031]) in the second device region, the first fin-type active region and the second fin-type active region extending in a first horizontal direction (X direction; [0030]);
a nanosheet stack (NSS (N1, N2, N3); [0036]-[0037]) disposed on each of the first fin-type active region and the second fin-type active region;
a gate line (160; [0032]) disposed above the first fin-type active region and the second fin-type active region, the gate line surrounding the nanosheet stack ([0044]) and extending across the first device region and the second device region and the device isolation region in a second horizontal direction (Y direction; [0032]) that crosses the first horizontal direction;
a first source/drain region (SD1; [0043]) in the first fin-type active region and a second source/drain region (SD2; [0043]) in the second fin-type active region, the first source/drain region and the second source/drain region being adjacent to the gate line and in contact with the nanosheet stack;
a spacer structure (118; [0052] and [0054]) covering a sidewall of the gate line and portions of the first source/drain region and the second source/drain region; and
an insulating liner (142; [0071]) covering the spacer structure and top surfaces of the first source/drain region and the second source/drain region.
Yoon does not disclose a protective insulating film disposed on the second source/drain region and exposing the first source/drain region.
Li teaches in Figs. 1A, 1D, 1E and related text a protective insulating film (122; [0030]) disposed on the second source/drain region (108P; [0021]) and exposing the first source/drain region (108N; [0020]).
Yoon and Li are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yoon with the specified features of Li because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a protective insulating film disposed on the second source/drain region and exposing the first source/drain region, as taught by Li, in order to increase longitudinal compressive stress in the channel region(s), thereby increasing the mobility of holes flowing in the channel region(s). Increasing the hole mobility in the channel region(s) of p-type field-effect transistors can improve the device performance (Li: [0016]).
Regarding claim 12, Yoon in view of Li disclose the integrated circuit device of claim 10.
Yoon does not disclose the protective insulating film is formed to a thickness of about 1 nanometer (nm) to about 3 nm in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction.
Li teaches in Fig. 1E and related text the protective insulating film (122; [0030] and [0032]) is formed to a thickness of about 1 nanometer (nm) to about 3 nm in a vertical direction (Z direction) that is perpendicular to the first horizontal direction (X direction) and the second horizontal direction (Y direction).
Yoon and Li are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yoon in view of Li with the specified features of Li because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the protective insulating film to a thickness of about 1 nanometer (nm) to about 3 nm in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction, as taught by Li, in order to adequately provide the longitudinal compressive stress in the channel region(s) to enhance (increase) the mobility of holes in the channel region(s) for improving performance of a p-type field-effect transistor (Li: [0032]).
Regarding claim 13, Yoon in view of Li disclose the integrated circuit device of claim 10.
Yoon does not disclose the protective insulating film includes a silicon nitride film.
Li teaches the protective insulating film (122; [0030]) includes a silicon nitride film.
Yoon and Li are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yoon in view of Li with the specified features of Li because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the protective insulating film to include a silicon nitride film, as taught by Li, in order to configure the protective insulating film to provide longitudinal compressive stress in the channel region(s) of p-type field effect transistors (Li: [0016] and [0030]).
Regarding claim 15, Yoon in view of Li disclose the integrated circuit device of claim 10.
Yoon does not disclose the protective insulating film is deposited on every facet of the second source/drain region.
Li teaches in Fig. 1A and related text the protective insulating film (122/122P; [0030]) is deposited on every facet of the second source/drain region (108P; [0021]).
Yoon and Li are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yoon in view of Li with the specified features of Li because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the protective insulating film on every facet of the second source/drain region, as taught by Li, in order to increase longitudinal compressive stress in the channel region(s), thereby increasing the mobility of holes flowing in the channel region(s). Increasing the hole mobility in the channel region(s) of p-type field-effect transistors can improve the device performance (Li: [0016]).
Regarding claim 16, Yoon in view of Li disclose an isolation film (Yoon: 112; Fig. 2C; [0033]) disposed on the second fin-type active region, wherein a composition of a topmost surface of the isolation film is different from a composition of the second source/drain region (the device isolation film 112 includes an oxide film, a nitride film, or a combination thereof as disclosed by Yoon in [0034], and the second source/drain region SD2 includes p-type doped SiGe as disclosed by Yoon in [0069]).
Regarding claim 17, Yoon in view of Li disclose an n-channel metal-oxide semiconductor (NMOS) transistor is formed in the first source/drain region and a p-channel MOS (PMOS) transistor is formed in the second source/drain region (Yoon: [0044] and [0069]).
Allowable Subject Matter
Claims 3, 11 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, individually or in combination, does not teach or suggest “the protective insulating film is disposed directly on the second source/drain region” as recited in claim 3, “a bottom surface of the protective insulating film is at a same vertical level as a top surface of the second source/drain region” as recited in claim 11, and “a height of a lowermost portion of the insulating liner above the second fin-type active region is greater than a height of a lowermost portion of the insulating liner above the first fin-type active region by a thickness of the protective insulating film” as recited in claim 14.
Claims 5 and 6 would be allowable if claim 5 were to be rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, individually or in combination, does not teach or suggest an insulating liner conformally covering a top surface of the protective insulating film as claimed in claim 5.
Claims 18 and 19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, individually or in combination, does not teach or suggest “an insulating liner covering a top surface of the first source/drain region, a top surface of the protective insulating film, and sidewalls of the plurality of spacer structures” and “a difference between a height of the insulating liner above the second fin-type active region and a height of the insulating liner above the first fin-type active region corresponds to a thickness of the protective insulating film” as recited in claim 18.
Claim 20 depends from allowable independent claim 18. Therefore, claim 20 would be allowable if amended to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
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/PETER M ALBRECHT/Primary Examiner, Art Unit 2811
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