DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/27/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 3, 5-12 and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US PG. Pub. 2016/0055403) in view of Iwata et al. (US Patent 5512712) and further in view of Chen (US PG. Pub. 2009/0236739).
Regarding claim 1 – Chou teaches a substrate structure (fig. 1D’ [title] Chou states, “substrate structure”), comprising: a substrate body (10 & 12) including a dielectric layer (10 [paragraph 0008] Chou states, “a board 10”) and a circuit layer (12 [paragraph 0009] Chou states, “a patterned metallic layer 12”) formed on the dielectric layer (10); a first insulating layer (13 [paragraph 0011] Chou states, “protective layer 13”) disposed on the substrate body (10) and formed with a plurality of openings (131 [paragraph 0010] Chou states, “holes 131”) exposing a portion of the circuit layer (12); and a second layer (14 [paragraph 0011] Chou states, “inkjet is used to form an applying layer 14 on the protective layer 13”) disposed on a portion of the first insulating layer (13), wherein the second layer (14) is arranged with a mark thereon (130’ [paragraph 0011] Chou states, “another protective pattern 130′ for forming the 2D barcode image”), and wherein the second layer (14) is free of any circuit layer (claimed structure shown in figure 1D’).
Chou fails to explicitly teach the second layer is a second insulating layer; and wherein the mark records all processing process records of the substrate structure that trace all current processing processes of the substrate structure.
Iwata teaches a substrate structure (fig. 6 [title] Iwata states, “printed wiring board having indications thereon covered by insulation”) having a second layer (30 & 40) being a second insulating layer (30 [columns 6 & 5 lines 7-9 & 34-35] Iwata states, “insulation coating 30 may be a photo-sensitive acrylic resin or a photo-sensitive epoxy…indications 40 may be an epoxy resin ink or an acrylic resin ink”) disposed on a portion of the first insulating layer (60 [column 7 lines 65-66] Iwata states, “wherein plating resist 60 and conductor circuits 20 are provided on a substrate 10”), wherein the second insulating layer (30 & 40) is arranged with a mark (40 [column 5 lines 33-35] Iwata states, “The indications 40 may be an epoxy resin ink or an acrylic resin ink”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the substrate structure with a second layer arranged with a mark thereon as taught by Chou with the second layer being explicitly a second insulating layer with a mark as taught by Iwata because Iwata states, “it is preferred to provide insulation coating 30 on the substrate 10 by using a photo-sensitive liquid resin and appropriately treating the liquid resin to cure. Advantages of using a photo-sensitive liquid resin include, among others: (1) improved capability of properly covering an uneven or rough surface such that the covered surface may become even or flat; (2) improved configuration precision of the covered surface 30; and (3) improved property of the printed wiring board” [columns 5 & 6 lines 65-7].
Chen teaches a second insulating layer (figs. 1-3, 114 [paragraph 0019] Chen states, “the substrate ID code 130 is burned in the solder mask 114”) arranged with a mark (fig. 3, 130) thereon, wherein the mark (130) records all processing process records of the substrate structure (see substrate structure shown in figure 1, 100) that trace all current processing processes of the substrate structure ([paragraph 0021] Chen states, “The substrate ID code 130 is chosen from a group of numbers, texts, symbols, figures, etc to show the production lot numbers of the substrate 110, inspection numbers, location numbers, substrate strip numbers, or other processing related numbers of the substrate 110 to quickly know the substrate information of production dates, production time, production lines, production equipment, and suppliers”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the substrate structure having a second insulating layer arranged with a mark thereon as taught by Chou in view of Iwata with the mark recording all processing process records of the substrate structure as taught by Chen because Chen states, “when failed or low yield semiconductor packages 100 were identified during FT or other packaging processes, the substrate ID code 130 hidden at the bottom of the semiconductor packages 100 can be used for quality control and for failure tracking and management.” [paragraph 0022].
Regarding claim 2 – Chou in view of Iwata and Chen teach the substrate structure of claim 1, wherein the mark (Iwata; fig. 6, 40 [column 4 line 32-33] Iwata states, “indications 40 of a colored insulation material”) wherein the mark is made of ink ([column 5 lines 33-35] Iwata states, “The indications 40 may be an epoxy resin ink or an acrylic resin ink”).
Regarding claim 3 – Chou in view of Iwata and Chen teach the substrate structure of claim 1, wherein the mark (Chen; fig. 3, 130) is a recess (see recesses shown in figure 3).
Regarding claim 5 – Chou in view Iwata and Chen teach the substrate structure of claim 1, wherein the mark (Iwata; fig. 6, 40) is text ([column 4 lines 45-46] Iwata states, “The indications 40 may include alphabetic letters, marks, numbers and signs”).
Regarding claim 6 – Chou in view Iwata and Chen teach the substrate structure of claim 1, wherein the mark (Chou; fig. 1D’, 130’) is a pattern ([paragraph 0011] Chou states, “protective pattern 130′ for forming the 2D barcode image”; a “barcode” is considered a pattern).
Regarding claim 7 – Chou in view of Iwata and Chen teach the substrate structure of claim 6, wherein the mark (Chou; fig. 1D’, 130’) is a two-dimensional barcode pattern ([paragraph 0011] Chou states, “protective pattern 130′ for forming the 2D barcode image”).
Regarding claim 8 – Chou in view Iwata and Chen teach the substrate structure of claim 1, wherein a vertical projected area of the second layer (Chou; fig. 1D’, 14) is stacked on the circuit layer (12; claimed structure shown in figure 1D’). Iwata teaches wherein the second layer is a second insulating layer as discussed in the rejection to claim 1.
Regarding claim 9 – Chou teaches a method of manufacturing a substrate structure (fig. 1D’ [title] Chou states, “substrate structure and method of manufacturing the same”), comprising: providing a substrate body (10 & 12) including a dielectric layer (10 [paragraph 0008] Chou states, “a board 10”) and a circuit layer (12 [paragraph 0009] Chou states, “a patterned metallic layer 12”) formed on the dielectric layer (10); disposing a first insulating layer (13 [paragraph 0011] Chou states, “protective layer 13”) on the substrate body (10), wherein the first insulating layer (13) is formed with a plurality of openings (131 [paragraph 0010] Chou states, “holes 131”) exposing a portion of the circuit layer (12); disposing a second layer (14 [paragraph 0011] Chou states, “inkjet is used to form an applying layer 14 on the protective layer 13”) on a portion of the first insulating layer (13), wherein the second layer (14) is free of any circuit layer (claimed structure shown in figure 1D’); and arranging a mark (130’ [paragraph 0011] Chou states, “another protective pattern 130′ for forming the 2D barcode image”) on the second layer (14).
Chou fails to explicitly teach wherein the second layer is an insulating layer; and wherein the mark records all processing process records of the substrate structure that trace all current processing processes of the substrate structure.
Iwata teaches a method of manufacturing a substrate structure (fig. 6 [title & column 1 lines 13-15] Iwata states, “printed wiring board having indications thereon covered by insulation…this invention also relates to a method for producing such printed wiring boards”) having a second layer (30) being a second insulating layer (30 [column 4 lines 33-34] Iwata states, “light transmittable insulating coating 30”) disposed on a portion of the first insulating layer (60 [column 7 lines 65-66] Iwata states, “wherein plating resist 60 and conductor circuits 20 are provided on a substrate 10”), wherein the second insulating layer (30) is arranged with a mark (40 [column 5 lines 33-35] Iwata states, “The indications 40 may be an epoxy resin ink or an acrylic resin ink”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the method of manufacturing a substrate structure with a second layer arranged with a mark thereon as taught by Chou with the second layer being explicitly a second insulating layer with a mark as taught by Iwata because Iwata states, “it is preferred to provide insulation coating 30 on the substrate 10 by using a photo-sensitive liquid resin and appropriately treating the liquid resin to cure. Advantages of using a photo-sensitive liquid resin include, among others: (1) improved capability of properly covering an uneven or rough surface such that the covered surface may become even or flat; (2) improved configuration precision of the covered surface 30; and (3) improved property of the printed wiring board” [columns 5 & 6 lines 65-7].
Chen teaches a second insulating layer (figs. 1-3, 114 [paragraph 0019] Chen states, “the substrate ID code 130 is burned in the solder mask 114”) arranged with a mark (fig. 3, 130) thereon, wherein the mark (130) records all processing process records of the substrate structure (see substrate structure shown in figure 1, 100) that trace all current processing processes of the substrate structure ([paragraph 0021] Chen states, “The substrate ID code 130 is chosen from a group of numbers, texts, symbols, figures, etc to show the production lot numbers of the substrate 110, inspection numbers, location numbers, substrate strip numbers, or other processing related numbers of the substrate 110 to quickly know the substrate information of production dates, production time, production lines, production equipment, and suppliers”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the method of manufacturing a substrate structure having a second insulating layer arranged with a mark thereon as taught by Chou in view of Iwata with the mark recording all processing process records of the substrate structure as taught by Chen because Chen states, “when failed or low yield semiconductor packages 100 were identified during FT or other packaging processes, the substrate ID code 130 hidden at the bottom of the semiconductor packages 100 can be used for quality control and for failure tracking and management.” [paragraph 0022].
Regarding claim 10 – Chou in view of Iwata and Chen teach the method of claim 9, wherein the mark (Iwata; fig. 6, 40 [column 4 line 32-33] Iwata states, “indications 40 of a colored insulation material”) wherein the mark is made of ink ([column 5 lines 33-35] Iwata states, “The indications 40 may be an epoxy resin ink or an acrylic resin ink”).
Regarding claim 11 – Chou in view of Iwata and Chen teach the method of claim 9, wherein the mark (Chen; fig. 3, 130) is a recess (see recesses shown in figure 3).
Regarding claim 12 – Chou in view of Iwata and Chen teach the method of claim 11, wherein the recess (Chen; fig. 3, see recesses shown in mark area 130) is formed on the second insulating layer (114) in a manner of laser ablation ([Abstract] Chen states, “A substrate ID code consisting of a plurality of laser marks is inscribed in the solder mask or in a portion of an encapsulant on the bottom surface away from the circuit to show the substrate lot number on the bottom surface”).
Regarding claim 14 – Chou in view Iwata and Chen teach the method of claim 9, wherein the mark (Iwata; fig. 6, 40) is text ([column 4 lines 45-46] Iwata states, “The indications 40 may include alphabetic letters, marks, numbers and signs”).
Regarding claim 15 – Chou in view Iwata and Chen teach the method of claim 9, wherein the mark (Chou; fig. 1D’, 130’) is a pattern ([paragraph 0011] Chou states, “protective pattern 130′ for forming the 2D barcode image”; a “barcode” is considered a pattern).
Regarding claim 16 – Chou in view of Iwata and Chen teach the method of claim 15, wherein the mark (Chou; fig. 1D’, 130’) is a two-dimensional barcode pattern ([paragraph 0011] Chou states, “protective pattern 130′ for forming the 2D barcode image”).
Regarding claim 17 – Chou in view Iwata and Chen teach the method of claim 9, wherein a vertical projected area of the second layer (Chou; fig. 1D’, 14) is stacked on the circuit layer (12; claimed structure shown in figure 1D’). Iwata teaches wherein the second layer is a second insulating layer as discussed in the rejection to claim 1.
Claim(s) 4 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Iwata et al. and Chen et al. as applied to claims 1 and 9 discussed above, and further in view of Matsuura et al. (US PG. Pub. 2022/0223456).
Regarding claim 4 – Chou in view of Iwata and Chen teach the substrate structure of claim 3, but fail to teach wherein a depth of the recess is 5 um to 10 um.
Matsuura teaches a substrate structure (fig. 4) having a mark (12a [paragraph 0034] Matsuura states, “the processed portion constituting the alignment mark itself may be the depressed portion 12a”) wherein the mark (12a) is a recess (see recess 12a) with a depth of the recess is 5 um to 10 um ([paragraph 0035] Matsuura states, “the maximum depth d of the depressed portion 12a is preferably 0.1 μm or more and 1000 μm or less, more preferably 0.5 μm or more and 800 μm or less, further preferably 1.0 μm or more and 500 μm or less, and particularly preferably 3.0 μm or more and 400 μm or less”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the substrate structure having a mark with a recess as taught by Chou in view of Iwata and Chen with the mark having a depth of the recess between 5um-10um as taught by Matsuura because Matsuura states regarding optimizing the depth of the recess, “When the maximum depth is within such a range, a decrease in the mechanical strength of the carrier is suppressed, and the deformation and cracking of the carrier during the manufacturing process can be effectively prevented” [paragraph 0035].
Regarding claim 13 – Chou in view of Iwata and Chen teach the method of claim 11, but fail to teach wherein a depth of the recess is 5 um to 10 um.
Matsuura teaches a mark (fig. 4, 12a [paragraph 0034] Matsuura states, “the processed portion constituting the alignment mark itself may be the depressed portion 12a”) wherein the mark (12a) is a recess (see recess 12a) with a depth of the recess is 5 um to 10 um ([paragraph 0035] Matsuura states, “the maximum depth d of the depressed portion 12a is preferably 0.1 μm or more and 1000 μm or less, more preferably 0.5 μm or more and 800 μm or less, further preferably 1.0 μm or more and 500 μm or less, and particularly preferably 3.0 μm or more and 400 μm or less”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the method of manufacturing a substrate structure having a mark with a recess as taught by Chou in view of Iwata and Chen with the mark having a depth of the recess between 5um-10um as taught by Matsuura because Matsuura states regarding optimizing the depth of the recess, “When the maximum depth is within such a range, a decrease in the mechanical strength of the carrier is suppressed, and the deformation and cracking of the carrier during the manufacturing process can be effectively prevented” [paragraph 0035].
Response to Arguments
Applicant's arguments filed 8/27/2026 have been fully considered but they are not persuasive.
Applicant argues regarding the rejections to independent claims 1 and 9, “There is no motivation for a person having ordinary skill in the art to apply the technical teachings of Iwata to modify the inkjet applied layer of Chou. Specifically, Iwata’s liquid resin coating is explicitly directed to smoothing out an “uneven or rough surface," which is a technical problem that does not arise in the inkjet deposition process disclosed by Chou. Therefore, a person having ordinary skill in the art would have no reasonable basis or motivation to combine these distinct manufacturing methodologies in the manner asserted ” [REMARKS page 6].
Examiner disagrees. Iwata states in columns 5-6 lines 65-7, “”(2) improved configuration precision of the covered surface 30”. Therefore the second insulating layer 30/40 and its specific insulating material of Iwata can be precisely located and patterned. The secondary reference Iwata is only relied up to teach that the second layer including the mark of the primary Chou can be made of an insulating layer. Precise patterning would appear to benefit the primary reference Chou and provides proper motivation for the 103 obviousness rejection. Additionally Examiner points to Iwata column 4 lines 41-43 that states, “The indications 40 can (partially) cover the conductor circuit 20 since the indications 40 of an insulation material do not hinder the performance of the conductive circuits 20”. Forming the second layer of an insulating material will prevent the mark from unintentionally shorting with other conductive parts of the substrate structure.
Applicant’s additional arguments with respect to claim(s) 1-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chou et al. (US PG. Pub. 2007/0241466) discloses a chip package.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
