Prosecution Insights
Last updated: October 26, 2026

Steven T Sawyer, USPTO Patent Examiner

Listed by the USPTO as SAWYER, STEVEN T

Tech Center 2800 • Art Units: 1765 2835 2841 2847 2896

This examiner grants 73% of resolved cases

Analysis

SAWYER, STEVEN T has 1054 resolved cases and an allowance rate of 72.6%. The median time to allowance is 884 days. Interviews correspond to a 30.4% lift in the allowance rate, providing a strong practical reason to consider examiner interviews when the application’s disputed issues can be addressed efficiently. The substantial resolved-case record gives this pattern useful weight for prosecution planning.

The listed companies are Samsung Electro-Mechanics Co., Ltd., Samsung Electronics Co., Ltd., and Panasonic Holdings Corporation. The listed firms are Morgan, Lewis & Bockius LLP (WA), SUGHRUE MION, PLLC, and Armis Intellectual Property Law, LLC. Counsel can use these organizations to understand the applicant and representative mix reflected in the docket.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

72.6%
Allow Rate
+4.6% vs TC avg
1,091
Total Applications
+30.4%
Interview Lift
884
Avg Prosecution Days
Based on 1054 resolved cases, 2023–2026

Rejection Statute Breakdown

0.2%
§101 Eligibility
24.2%
§102 Novelty
64.1%
§103 Obviousness
9.7%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18754916 PRINTED CIRCUIT BOARD STRUCTURE CONTAINING THERMAL INTERFACE MATERIAL AND ELECTRONIC DEVICE INCLUDING THE SAME Non-Final OA SAMSUNG ELECTRONICS CO., LTD.
18865595 MOUNTING SUBSTRATE AND MOUNTING SUBSTRATE MANUFACTURING METHOD Non-Final OA Panasonic Intellectual Property Management Co., Ltd.
18462220 BRIDGE PRINTED CIRCUIT BOARD EMBEDDED WITHIN ANOTHER PRINTED CIRCUIT BOARD Non-Final OA Intel Corporation
18925509 CIRCUIT MODULE AND MANUFACTURING METHOD THEREFOR Non-Final OA Murata Manufacturing Co., Ltd.
18267051 CONNECTION CARRIER, OPTOELECTRONIC DEVICE AND METHOD FOR PRODUCING A CONNECTION CARRIER Final Rejection ams-OSRAM International GmbH
18692985 CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE COMPRISING SAME Non-Final OA LG INNOTEK CO., LTD.
19002414 GLASS CORE LAMINATE STRUCTURE AND PRODUCTION METHOD FOR GLASS CORE LAMINATE STRUCTURE Non-Final OA TOPPAN HOLDINGS INC.
18894060 PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD FOR THE SAME Non-Final OA SAMSUNG ELECTRO-MECHANICS CO., LTD.
18734089 PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME Non-Final OA SAMSUNG ELECTRO-MECHANICS CO., LTD.
18666165 CIRCUIT BOARD AND METHOD OF FABRICATING CIRCUIT BOARD Final Rejection SAMSUNG ELECTRO-MECHANICS CO., LTD.

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Frequently Asked Questions

What is examiner Steven T Sawyer's allowance rate?

72.6% of resolved applications examined by Steven T Sawyer were allowed (1,054 resolved cases), compared with 52.6% across Art Unit 1765 over the last five years.

Does an interview help with examiner Steven T Sawyer?

This examiner's interview lift is +30.4 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.

How long does examiner Steven T Sawyer take to allow a patent?

Applications allowed by Steven T Sawyer took 884 days on average from filing to allowance.

Which art unit does examiner Steven T Sawyer work in?

Steven T Sawyer examines applications in Art Unit 1765 in Tech Center 2800 (Semiconductors, Circuits & Optics).

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