DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of applicant’s Amendment, filed 24 July 2026. The changes and remarks disclosed therein have been considered.
Claims 11 and 26 have been cancelled by Amendment. Therefore, claims 1-10, 12-14, 21-25 are pending in the application.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “a first memory cell in a first pillar is used to represent a least significant bit (LSB), and at least two second memory cells of the first pillar are used to represent a most significant bit (MSB)”, as recited in claim 13, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 9’s “a controller” that is “configured to” perform recited operations;
Apparatus claims 21’s “select transistor” that is “configured to” perform recited operations.
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 3, 9-10 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 3, 9-10 are recites the limitation "the stored weights" in claims 1, 9; “…the array” in claims 3, 10. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-12, 21-26 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al (US 2022/0398438 A1 hereinafter “Zhang”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Zhang, for example in Figs. 1-20, discloses a device (e.g., memory device 1450; in Fig. 14 related in Figs. 1-13, 15-20) comprising:
a memory cell array (e.g., NOR strings; in Figs. 16, 18 related in Figs. 1-15, 17, 19-20) having stacked memory cells (e.g., 3D NOR string 1600; in Figs. 16-18 related in Figs. 1-15, 19-20), each memory cell (e.g., memory cell 1801; in Fig. 18 related in Figs. 1-17, 19-20) configured to store a weight (e.g., weight W1,1; in Fig. 18 related in Figs. 1-17, 19-20); and
select lines (e.g., via VSG_1 and VSG_2; in Fig. 18 related in Figs. 1-17, 19-20) configured to control select transistors (e.g., SG1 and SG2; in Fig. 18 related in Figs. 1-17, 19-20), and to encode an input pattern (e.g., Vt_1,1; in Fig. 18 related in Figs. 1-17, 19-20) to multiply by the stored weights (via the tables; in Figs. 19A-D related in Figs. 1-18, 20).
The structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 2, Zhang, for example in Figs. 1-20, discloses further comprising: local digit lines (e.g., LBLs and LSLs; in Fig. 18 related in Figs. 1-17, 19-20) connected to terminals of the memory cells (e.g., memory cells 1801; in Fig. 18 related in Figs. 1-17, 19-20), the local digit lines extending vertically (see for example in Fig. 18 related in Figs. 1-17, 19-20); and global digit lines running horizontally in a direction orthogonal to the select lines (e.g., GBL and GSL; in Fig. 18 related in Figs. 1-17, 19-20), wherein the select transistors connect the global digit lines to the local digit lines (see for example in Fig. 18 related in Figs. 1-17, 19-20), and the global digit lines are used to accumulate output currents from the memory cells (via block 1850; in Fig. 18 related in Figs. 1-17, 19-20). Also, the structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 3, Zhang, for example in Figs. 1-20, discloses further comprising wordlines connected to gates of the memory cells (e.g., WLs; in Fig. 18 related in Figs. 1-17, 19-20), wherein the wordlines are configured to select at least a portion of the array for use in multiplication (see for example in Figs. 12, 18-19 related in Figs. 1-11, 13-17, 20). Also, the structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 4, Zhang, for example in Figs. 1-20, discloses wherein the wordlines run horizontally in a direction parallel to the select lines (see for example in Fig. 18 related in Figs. 1-17, 19-20). Also, the structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 5, Zhang, for example in Figs. 1-20, discloses wherein the memory cells of the array are arranged in horizontal tiers that are stacked vertically, and the wordlines are further configured to select at least one tier for the multiplication (see for example in Figs. 15-17 related in Figs. 1-14, 18-20). Also, the structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 8, Zhang, for example in Figs. 1-20, discloses wherein each memory cell is configured to store multiple bits (see for example in Figs. 18-19 related in Figs. 1-17, 20). Also, the structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding Independent Claim 9, Zhang, for example in Figs. 1-20, discloses an apparatus (e.g., memory device 1450; in Fig. 14 related in Figs. 1-13, 15-20) comprising:
a memory cell array (e.g., NOR strings; in Figs. 16, 18 related in Figs. 1-15, 17, 19-20) having memory cells arranged vertically (see for example in Figs. 15-16, 18 related in Figs. 1-14, 17, 19-20), each memory cell (e.g., memory cell 1801; in Fig. 18 related in Figs. 1-17, 19-20) configured to store a weight (e.g., the weight W1,1; in Fig. 18 related in Figs. 1-17, 19-20); and
a controller (e.g., control 560 operated as read/write operation by selecting or unselecting the bit lines and word lines; in Fig. 5 related in Figs. 1-4, 6-20) configured to dynamically select or deselect tiers of the array to map to an input to multiply by the stored weights (e.g., select gate SG1/SG2 terminal received a voltage or signal; in Figs. 15-16 related in Figs. 1-14, 17- 20).
The structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 10, Zhang, for example in Figs. 1-20, discloses further comprising: local digit lines connected to terminals of the memory cells, the local digit lines extending vertically (e.g., LBLs and LSLs; in Fig. 18 related in Figs. 1-17, 19-20); select transistors connected to the local digit lines (e.g., SG1 and SG2; in Fig. 18 related in Figs. 1-17, 19-20); and select lines configured to control the select transistors (.g., via VSG_1 and VSG_2; in Fig. 18 related in Figs. 1-17, 19-20) to select a subset of the array for use in multiplication (see for example in Fig. 18 related in Figs. 1-17, 19-20). Also, the structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 11, Zhang, for example in Figs. 1-20, discloses further comprising a controller configured to dynamically select or deselect tiers of the array to map to the input (see for example in Fig. 12 related in Figs. 1-11, 13-20). Also, the structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 12, Zhang, for example in Figs. 1-20, discloses wherein the memory cells of the array are arranged in tiers that are stacked vertically (see for example in Fig. 18 related in Figs. 1-17, 19-20), and output currents from the memory cells are accumulated from multiple tiers of the array (via block 1850; in Fig. 18 related in Figs. 1-17, 19-20). Also, the structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding Independent Claim 21, Zhang, for example in Figs. 1-20, discloses a device (e.g., memory device 1450; in Fig. 14 related in Figs. 1-13, 15-20) comprising: a select transistor configured to receive an input pattern for multiplication (e.g., SG1/SG2; in Figs. 15-16 related in Figs. 1-14, 17-20); and memory cells with current terminals of each memory cell (see for example in Fig. 18 related in Figs. 1-17, 19-20) connected to a digit line (e.g., LBLs and LSLs; in Fig. 18 related in Figs. 1-17, 19-20) by the select transistor (e.g., SG2/SG1; in Fig. 18 related in Figs. 1-17, 19-20).
The structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 22, Zhang, for example in Figs. 1-20, discloses further comprising a semiconductor substrate (implied NOR string formed over a substrate; in Figs. 15-17 related in Figs. 1-14, 18-20), wherein the memory cells are stacked vertically above the semiconductor substrate (e.g., vertical NOR strings; in Figs. 15-17 related in Figs. 1-14, 18-20). Also, the structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 23, Zhang, for example in Figs. 1-20, discloses wherein the digit line is a common global digit line (e.g., e.g., GBL/GSL; in Fig. 18 related in Figs. 1-17, 19-20). Also, the structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 24, Zhang, for example in Figs. 1-20, discloses wherein the memory cells are configured to store weights (e.g., weight W1,1; in Fig. 18 related in Figs. 1-17, 19-20), the device further comprising a controller (e.g., 1450; in Fig. 14 related in Figs. 1-13, 15-20) configured to perform multiplication (via the tables; in Figs. 19A-D related in Figs. 1-18, 20) using output currents accumulated from the memory cells (see for example in Figs. 18 related in Figs. 1-17,19-20). Also, the structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 25, Zhang, for example in Figs. 1-20, discloses further comprising a select line that controls the select transistor (e.g., via VSG_1 / VSG_2; in Fig. 18 related in Figs. 1-17, 19-20), wherein: the multiplication provides a result from multiplication of an input pattern by the weights stored in the memory cells (see for example in Figs. 18-19 related in Figs. 1-17, 20); and the input pattern is applied by varying a voltage on the select line (see for example in Figs. 18-19 related in Figs. 1-17, 20). Also, the structure in of prior art (Zhang) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (US 2022/0398438 A1 hereinafter “Zhang”) in view of Harari (US 10,475,812 B2).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 6, Zhang, for example in Figs. 1-20, discloses the claimed invention as discussed above. However, Zhang is silent with regard to each select transistor is located above the memory cells of a respective pillar.
In the same field of endeavor, Harari, for example in Figs. 1-8, discloses each select transistor (e.g., selector 311; in Figs. 3a, 3b related in Figs. 1-2, 4-8) is located above the memory cells of a respective pillar (see for example in Figs. 5a, 5b related in Figs. 1-4, 6-8).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Zhang such as compute in memory three-dimensional non-volatile NOR memory for neural networks (see for example in Figs. 1-20 of Zhang) by incorporating the teaching of Harari such as three-dimensional vertical NOR flash thin-film transistor strings (see for example in Figs. 1-8 of Harari). In order to provide a memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate (Harari, see abstract).
The structure in of prior art (Zhang and Harari) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 7, the above Zhang/Harari, combination discloses wherein the select transistors are first select transistors (see for example in Figs. 15-19 related in Figs. 1-14, 20 of Zhang and also see in Figs. 3a, 3b related in Figs. 1-2, 4-8 of Harari, as discussed above), the device further comprising: first local digit lines connected to first terminals of the memory cells, the first local digit lines extending vertically (see for example in Figs. 15-19 related in Figs. 1-14, 20 of Zhang and also see in Figs. 3a, 3b related in Figs. 1-2, 4-8 of Harari, as discussed above); second local digit lines connected to second terminals of the memory cells, the second local digit lines extending vertically (see for example in Figs. 15-19 related in Figs. 1-14, 20 of Zhang and also see in Figs. 3a, 3b related in Figs. 1-2, 4-8 of Harari, as discussed above); and second select transistors connected to the second local digit lines, wherein each second select transistor is located below the memory cells of a respective pillar (see for example in Figs. 15-19 related in Figs. 1-14, 20 of Zhang and also see in Figs. 3a, 3b related in Figs. 1-2, 4-8 of Harari, as discussed above). Also, the structure in of prior art (Zhang and Harari) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (US 2022/0398438 A1 hereinafter “Zhang”) in view of Choi et al (US 11,081,148 B2 hereinafter “Choi”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 13, Zhang, for example in Figs. 1-20, discloses the claimed invention as discussed above. However, Zhang is silent with regard to wherein a first memory cell in a first pillar is used to represent a least significant bit (LSB), and at least two second memory cells of the first pillar are used to represent a most significant bit (MSB).
In the same field of endeavor, Choi, for example in Figs. 1-9, discloses wherein a first memory cell in a first pillar is used to represent a least significant bit (LSB) (e.g., B1; in in Figs. 5 related in Figs. 1-4, 6-9), and at least two second memory cells of the first pillar are used to represent a most significant bit (MSB) (e.g., B3 and B2; in Figs. 5A-E related in Figs. 1-4, 6-9).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Zhang such as compute in memory three-dimensional non-volatile NOR memory for neural networks (see for example in Figs. 1-20 of Zhang) by incorporating the teaching of binary weighted voltage encoding scheme for supporting multi-bit input precision (see for example in Figs. 1-9 of Choi), for the purpose of controlling the non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell (Choi, see abstract).
The structure in of prior art (Zhang and Harari) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 14, the above Zhang/Choi, combination discloses wherein a combined output current of the second memory cells is an integer multiple of an output current of the first memory cell (see for example in Figs. 15-19 related in Figs. 1-14, 20 of Zhang and also see in Figs. 5A-E related in Figs. 1-4, 6-9 of Choi). Also, the structure in of prior art (Zhang and Harari) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Response to Arguments
Applicant's arguments filed 24 July 2026 have been fully considered but they are not persuasive.
Applicant directed to figures 7, 15 depicts memory cells may represent an LSB and MSB, as recited in claim 13 (see remarks file 24 July 2026, second paragraph on page 1).
In response, LSB and MSB are not found in Figures 7, 15. Therefore, the drawings are objected to under 37 CFR 1.83(a) because they fail to show “…a least significant bit (LSB)…a most significant bit (MSB)” as described in the specification.
Applicant argument against over U.S.C 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter. The rejection’s indication of the claim limitation “the stored weights” in claims 1, 9; and the claim limitation “…the array” in claims 3, 10; is not persuasive.
Applicant presents multiple paragraphs from the specification as “…import claim limitations from the specification” see MPEP 2111.01.
Applicant argues that the reference of Zhang does not discloses “select lines configured to control select transistors, and to encode an input patter to multiply by the store weights”, as recited in claim 1 (see remarks file 24 July 2026, see page 3).
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Prior Art
In response to applicant’s argument, the recitation “select lines configured to control select transistors” as show in Figs. 15 and 16 of Zhang, to encode an input pattern to multiply (implied to apply a voltage, signal to the selected memory cell as present a functional language) by the store weights (as proprogram/write a bit or multiple-bit per cell). the question for applicant is, what does the invention require in order to achieve this result. In other words, what inside the claim does the claimed "apparatus" have that yields the result of an input pattern to multiply by the store weights. The structure in of the prior art (Zhang) is substantially identical to structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Applicant argues that the reference of Zhang does not discloses “a controller configured to dynamically select or deselect tiers of the array to map to an input to multiply by stored weights”, as recited in claim 9 (see remarks file 24 July 2026, on page 4).
In response to applicant’s argument to a controller (e.g., 560; in Fig. 5 of Zhang) can perform a read/write operation to the memory cell array, to write/store the bits in the memory cells by selecting and unselecting a bit line and word line. See MPEP2112.01(I) and MPEP2114(II).
Applicant argues that the reference of Zhang does not disclose “a select transistor configured to recive an input pattern for multiplication” as recited in claim 21 (see remarks file 24 July 2026, page 4).
In response to applicant’s argument to a select gate transistor of Zhang can received voltage or signal at the gate terminal to perform read/write operation in the memory cell array. See MPEP2112.01(I) and MPEP2114(II).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/THA-O H BUI/ Primary Examiner, Art Unit 2825 09/17/20263
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