DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tang et al. (20210327482).
With regard to claim 1, Tang et al. disclose a semiconductor device (for example, see fig. 9), comprising:
a first array (referred to as “S1” by examiner’s annotation shown in fig. 9 below) of memory cells comprising at least a first memory cell (referred to as “M1” by examiner’s annotation shown in fig. 9 below), wherein the first memory cell (M1) comprises a first vertical transistor (T1) and a storage structure (a memory structure 110, having a storage capacity; for example, see paragraph [0061]) coupled to the first vertical transistor (T1) in a first direction (D1), and wherein the first array (S1) of memory cells is in a first area (referred to as “A1” by examiner’s annotation shown in fig. 9 below) of a first semiconductor structure (a first semiconductor structure forming in the first areas A1, A2 as annotated in fig. 9 below) of the semiconductor device (fig. 9); and
a second array (referred to as “S2” by examiner’s annotation shown in fig. 9 below) of memory cells comprising at least a second memory cell (referred to as “M2” by examiner’s annotation shown in fig. 9 below), wherein the second memory cell (M2) comprises a second vertical transistor (T2) in a second area (referred to as “A2” by examiner’s annotation shown in fig. 9 below) of the first semiconductor structure (the first semiconductor structure forming in the first areas A1, A2 as annotated in fig. 9 below), and wherein the second area (A2) is adjacent to the first area (A1) in a second direction (D2) perpendicular to the first direction (D1).
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (12676189).
With regard to claim 1, Lee discloses a semiconductor device (for example, see fig. 7, 15B), comprising:
a first array (referred to as “S1” by examiner’s annotation shown in fig. 7 below) of memory cells comprising at least a first memory cell, wherein the first memory cell (M1) comprises a first vertical transistor (referred to as “T1” by examiner’s annotation shown in fig. 7 below) and a storage structure (CAP) coupled to the first vertical transistor (T1) in a first direction (D3), and wherein the first array (S1) of memory cells is in a first area (referred to as “A1” by examiner’s annotation shown in fig. 7 below) of a first semiconductor structure (W1, W2) of the semiconductor device (fig. 7, or 15B); and
a second array (referred to as “S2” by examiner’s annotation shown in fig. 7 below) of memory cells comprising at least a second memory cell, wherein the second memory cell comprises a second vertical transistor (referred to as “T2” by examiner’s annotation shown in fig. 9 below) in a second area (referred to as “A2” by examiner’s annotation shown in fig. 9 below) of the first semiconductor structure (W1, W2), and wherein the second area (A2) is adjacent to the first area (A1) in a second direction (D2) perpendicular to the first direction (D3).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2,4, 5, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (12676189) in view of Chang et al. (20250070054).
With regard to claim 2, Lee discloses an access transistor (TR) coupled to the second vertical transistor (T2), and wherein the access transistor (TR) is in a second semiconductor structure (W1) of the semiconductor device.
Lee and Chen et al. do not clearly disclose the memory cell is one-time-programmable memory cell.
However, Chang et al. disclose the memory cell (103) is one-time-programmable memory cell. (for example, see paragraphs [0026], [0092], and claim 12, fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Lee and Chen et al.’s device to have the memory cell is one-time-programmable memory cell as taught by Chang et al. in order to enhance a high generation efficiency of a output for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 4, Lee discloses a source of the access transistor (the access transistor TR inherently having a source) is coupled (directly or indirectly) to a source (S) of the second vertical transistor (T2).
With regard to claim 5, Lee discloses the second array (S2) of memory cells comprises a first group of vertical transistors (SW) coupled to a first program line (the wiring structure ms functions as a first program line) through a gate (330) of each vertical transistor (SW) of the first group of vertical transistors; the first group of vertical transistors (SW) comprises the second vertical transistor (T2); and the first group of vertical transistors (SW) is comprised in a first array of vertical transistors in the second area (A2) of the first semiconductor structure.
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With regard to claim 7, Lee discloses the second array of memory cells further comprises a second group of vertical transistors (SW) coupled to a second program line (one of wirings ms functions as a second program line) through a gate (330) of each vertical transistor (SW) of the second group of vertical transistors (SW); and the second group of vertical transistors (SW) is comprised in a second array of vertical transistors (SW) in the second area (A2) of the first semiconductor structure.
7. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Gomes et al. (12604481) in view of Lee (12676189) and further in view of Chang et al. (20250070054).
With regard to claim 11, Gomes et al. disclose a semiconductor device (for example, see fig. 4), comprising:
an array of memory cells (cell levels 391, 391’ functions having memory cells wherein cells having transistors 382, 382’, and capacitors 20, 20’) comprising at least a memory cell (a memory cell having transistor 382, capacitor 20),
wherein the memory cell comprises a transistor (382) in a first semiconductor structure (an IC semiconductor structure 401 functions as a first semiconductor structure) of the semiconductor device and an access transistor (382’) in a second semiconductor structure (an IC semiconductor structure 401’ functions as a second semiconductor structure) of the semiconductor device, wherein the first semiconductor structure (401) and the second semiconductor structure (401’) are bonded through a hybrid bonding structure (a structure having hybrid bond interface HBI, fig. 4, functions as a hybrid bonding structure), and wherein the access transistor (382’) is coupled to the transistor (382).
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Gomes et al. do not clearly disclose the transistor in the first semiconductor structure is a vertical transistor.
However, Lee discloses the transistor (SW) in the first semiconductor structure (W2) is a vertical transistor. (for example, see fig. 7).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Gomes et al.’s device to have a transistor of the memory cell is a vertical transistor as taught by Lee in order to reduce a leakage current source in the transistor for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Gomes et al. and Lee do not clearly disclose the memory cells are one-time-programmable memory cells.
However, Chang et al. disclose the memory cells (103) are one-time-programmable memory cells. (for example, see paragraphs [0026], [0092], and claim 12, fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Gomes et al. and Lee’s device to the memory cells are one-time-programmable memory cells as taught by Chang et al. in order to enhance a high generation efficiency of a output for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Claims 18 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (12676189) in view of Chen et al. (10664239) and further in view of Chang et al. (20250070054).
With regard to claim 18, Lee discloses a method for forming a semiconductor device (for example, see figs. 7, 15B), comprising:
forming a first vertical transistor (SW) in a first area (referred to as “A1” by examiner’s annotation shown in fig. 7 below) of a first semiconductor structure (a semiconductor structure W2 functions as a first semiconductor structure) of the semiconductor device (the device of figs. 7, 15B), wherein the first vertical transistor (SW) comprises a first semiconductor body (a semiconductor body having a source S and drain D) and a first gate structure (a gate structure 330 as shown in fig. 7 below, or a gate structure as shown in fig. 15B) in contact with at least one side of the first semiconductor body (the semiconductor body having a source S and drain D);
forming a transistor (TR) in a second semiconductor structure (a semiconductor structure W1 functions as a second semiconductor structure) of the semiconductor device (the device of figs. 7, 15B); and
bonding the first semiconductor structure (W2) and the second semiconductor structure (W1) through a hybrid bonding structure (a hybrid bonding structure 140, 350; for example, see column 13, lines 43 – 45), wherein the first vertical transistor (SW) is coupled to the transistor (TR) through the hybrid bonding structure (140, 350).
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Lee does not clearly disclose the transistor is an anti-fuse capacitor.
However, Chen et al. disclose the transistor (a transistor having a gate 106a, and a gate dielectric layer 106b) is an anti-fuse capacitor. (for example, see claim 2, fig. 1).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Lee’s device to have the transistor is an anti-fuse capacitor as taught by Chen et al. in order to provide a high voltage to program of the device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Lee and Chen et al. do not clearly disclose the memory cells are one-time-programmable memory cells.
However, Chang et al. disclose the memory cells (103) are one-time-programmable memory cells. (for example, see paragraphs [0026], [0092], and claim 12, fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Lee and Chen et al.’s device to have the memory cells are one-time-programmable memory cells as taught by Chang et al. in order to enhance a high generation efficiency of a output for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 19, Lee discloses forming a second vertical transistor (referred to as “T2” by examiner’s annotation shown in fig. 7 below) in a second area (referred to as “A2” by examiner’s annotation shown in fig. 7 below) of the first semiconductor structure (W2), wherein the second vertical transistor (T2) comprises a second semiconductor body (another semiconductor body having other source/drain regions S/D) and a second gate structure (another gate electrode 330) in contact with at least one side of the second semiconductor body; and forming a storage structure (CAP) coupled to the second vertical transistor (T2) along a first direction (D3), wherein the second area (A2) is adjacent to the first area (A1) in a second direction (D2) perpendicular to the first direction (D3).
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With regard to claim 20, Lee discloses the first vertical transistor (T1 as annotated in fig. 7 above) and the second vertical transistor (T2 as annotated in fig. 7 above) are formed during a same operation (forming in the same structure and there is inherently a same operation) comprising: forming the first semiconductor body of the first vertical transistor (T1) in the first area (A1) of the first semiconductor structure and the second semiconductor body of the second vertical transistor (T2) in the second area (A2) of the first semiconductor structure, wherein the first semiconductor body and the second semiconductor body are formed on a first side (a bottom side) of the first semiconductor structure (W2); and forming the first gate structure (330) of the first vertical transistor (T1) and the second gate structure (330) of the second vertical transistor (T2).
Allowable Subject Matter
9. Claims 3, 6, 8 – 10, 12 - 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3, 6, 8 – 10, 12 - 17 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the second memory cell is a one-time-programmable (OTP) memory cell, the second vertical transistor is an access transistor of the OTP memory cell, the OTP memory cell further comprises an anti-fuse capacitor coupled to the second vertical transistor, and the anti-fuse capacitor is in a second semiconductor structure of the semiconductor device as recited in claim 3, each vertical transistor of the first group of vertical transistors is coupled to a corresponding access transistor in the second semiconductor structure through a first terminal of the vertical transistor; and a second terminal of the vertical transistor is floating as recited in claim 6, the first group of vertical transistors is comprised in a same row or a same column of the first array of vertical transistors; and a gate of each vertical transistors of the first group of vertical transistors is part of a same connection line of the first array of vertical transistors as recited in claim 8, the semiconductor device further comprises an array of dynamic random-access memory (DRAM) cells comprising at least a DRAM cell, wherein the DRAM cell comprises a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction, and wherein the array of DRAM cells is in a first area of a first semiconductor structure of the semiconductor device; the vertical transistor of the OTP memory cell is a second vertical transistor in a second area of the first semiconductor structure; and the second area is adjacent to the first area in a second direction perpendicular to the first direction as recited in claim 12.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
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