DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 23, 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-8, 13-15, and 18-21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Application Publication No. 2016/0172437 A1 to Masuda (“Masuda”). As to claim 1, Masuda discloses a semiconductor device comprising: an n-type silicon carbide (SiC) layer (21, 28) having an active region (20E) with a plurality of transistor elements (101, 102) formed therein, an outer peripheral region (20T) surrounding the active region (20E), and an outer end surface; a plurality of electrodes (50) selectively formed on the n-type SiC layer (21, 28) and electrically connected to the plurality of transistor elements (101, 102); a first insulating film (31 right) disposed under and overlapped by a portion of one of the plurality of electrodes (50), the first insulating film (31 right) extending toward the outer end surface of the n-type SiC layer (21, 28); a second insulating film (31 left) disposed under and overlapped by a portion of the one of the plurality of electrodes (50); a surface insulating film (60, 61) covering at least part (51) of the one of the plurality of electrodes (50), the first insulating film (31 right) and the second insulating film (31 left), wherein the surface insulating film (60, 61) extends to and contacts the n-type SiC layer (21, 28) in the outer peripheral region (20T) and reaches the outer end surface and includes a step (in 70) that contacts both an edge of the first insulating film (31 right) and the n-type SiC layer (21, 28) in the outer peripheral region (20T), and the surface insulating film (60, 61) includes a bottom portion (at 70a) buried in a recess (70) formed in the n-type SiC layer (21, 28) between the step (in 70) and the outer end surface, the bottom portion (at 70a) contacting an inner surface of the recess (70) at a depth below a bottom surface of the first insulating film (31 right) (See Fig. 1, Fig. 8, ¶ 0029, ¶ 0030, ¶ 0032, ¶ 0035, ¶ 0036, ¶ 0039, ¶ 0042, ¶ 0045-¶ 0053, ¶ 0056-¶ 0058, ¶ 0061, ¶ 0071, ¶ 0080). As to claim 2, Masuda further discloses wherein the electrodes (50) include a first pad electrode (51) electrically connected to at least one first electrode (23) of the plurality of transistor elements (101, 102) and a second pad electrode (51) electrically connected to at least one second electrode (23) of the plurality of transistor elements (101, 102) (See ¶ 0049). As to claim 3, Masuda further discloses wherein in cross-sectional view, a contact width of the step with the n-type SiC layer (21, 28) in a direction toward the outer end surface of the n-type SiC layer (21, 28) is narrower than a width of the first contact portion in the same direction (See Fig. 1, Fig. 8).
As to claim 5, Masuda further discloses wherein in a thickness direction of the n-type SiC layer (21, 28), a thickness of the surface insulating film (60, 61) in an area directly above the recess (70) is thicker than a thickness of the surface insulating film (60, 61) in an area other than the area directly above the recess (70) (See Fig. 8).
As to claim 6, Masuda further discloses wherein a dicing region is formed at an edge of the SiC layer (21, 28), and the SiC layer (21, 28) includes a second conductivity type region (27a) formed in a first conductivity type region (21 adjacent PS) of the dicing region (See Fig. 8). As to claim 7, Masuda discloses further comprising a termination structure having an impurity region (27a) of the second conductivity type formed outside the electrodes (50) in the SiC layer (21, 28) wherein a width (F) of the second conductivity type region (27a) is greater than or equal to the difference between a width (D) of the dicing region and a width which is twice as large as a width (E) of a depletion layer extending from the termination structure (See Fig. 8) (Notes: the limitation is met by the recited physical structures, where the depletion layer is determined by specific applied bias and/or doping concentrations).
As to claim 8, Masuda further discloses wherein a breakdown voltage value (BV) of the semiconductor device is 1000 V or greater (See ¶ 0046).
As to claim 13, Masuda further discloses wherein the surface insulating film (60, 61) includes an organic insulating layer of a polyimide-based material (See ¶ 0061). As to claim 14, Masuda further discloses wherein a MOSFET (101, 102) is formed in the n-type SiC layer (21, 28) as at least one of the plurality of the transistor elements (101, 102), and one of the plurality of electrodes (50) includes a source electrode (51) electrically connected to a source (23), which is a part of the MOSFET (101, 102) through which the ON-current flows and a gate electrode (32) configured to control a switching operation of the MOSFET (101, 102) (See Fig. 1, Fig. 8, ¶ 0049). As to claim 15, Masuda further disclose wherein the MOSFET (101, 102) has a planar-gate structure (See Fig. 1, Fig. 8) (Notes: the planar gate surface meets the limitation). As to claim 18, Masuda further discloses wherein at least one of the plurality of the transistor elements (101, 102) has a first portion (22) of a second conductivity type formed on a surface portion of the SiC layer (21, 28) and a second portion (24) of the second conductivity type formed on a surface portion of the first portion (22) and having an impurity concentration higher than that of the first portion (22), a contact hole (at P2) is formed between the first insulating film (31 right) and the second insulating film (31 left) such that the second portion (24) of the transistor element (101, 102) is exposed from the contact hole (at P2), and at least one of the electrodes (50) is electrically connected to the second portion (24) of the transistor element (101, 102) through the contact hole (at P2) (See Fig. 1, Fig. 8, ¶ 0047, ¶ 0048, ¶ 0049).
As to claim 19, Masuda further discloses wherein the surface insulating film (60, 61) has an end surface which is flush with the outer end surface of the SiC layer (21, 28) (See Fig. 1, Fig. 8).
As to claim 20, Masuda further discloses, wherein the surface insulating film (60, 61) has a flat top surface near the outer end surface of the SiC layer (21, 28) (See Fig. 1, Fig. 8). As to claim 21, Masuda discloses further comprising: a p-type termination structure (22, 26) formed in the n-type SiC layer (21, 28), wherein the plurality of electrodes (50) include a portion (right over first insulating film) that overlaps the first insulating film (31 right) to define an overlapped region (at 22, 23), and the p-type termination structure (22, 26) extends only partway into the overlapped region (at 22, 23) (See Fig. 8) (Notes: the p-type termination structure 22, 26 extends beyond the first insulating film to be only partway into the overlapped region).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2016/0172437 A1 to Masuda (“Masuda”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2014/0197422 A1 to Wada et al. (“Wada”). The teaching of Masuda has been discussed above. As to claim 9, although Masuda discloses an impurity concentration of the first conductivity type of the SiC layer (21, 28) (See Fig. 1, Fig. 8), Masuda does not further disclose wherein the impurity concentration of the first conductivity type of the SiC layer is 1x1016 cm-3 or less, and a thickness of the SiC layer is 5 μm or greater. However, Wada does disclose wherein the impurity concentration of the first conductivity type of the SiC layer (12) is 1x1016 cm-3 or less, and the thickness of the SiC layer (12) is 5 μm or greater (See Fig. 1, ¶ 0057, ¶ 0058). In view of the teaching of Wada, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Masuda to have wherein the impurity concentration of the first conductivity type of the SiC layer is 1x1016 cm-3 or less, and the thickness of the SiC layer is 5 μm or greater because these parameters determine the electric field relaxing region (See ¶ 0057, ¶ 0058).
Claims 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2016/0172437 A1 to Masuda (“Masuda”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2002/0052077 A1 to Tee et al. (“Tee”). The teaching of Masuda has been discussed above. As to claim 10, although Masuda discloses the electrodes (50) (See Fig. 1, Fig. 8), Masuda does not further disclose wherein the electrodes include a laminate structure represented by Ti/TiN/AI-Cu. However, Tee does disclose wherein the electrodes (36) include a laminate structure represented by Ti/TiN/Al-Cu (See Fig. 10, ¶ 0031). In view of the teaching of Tee, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Masuda to have wherein the electrodes include a laminate structure represented by Ti/TiN/AI-Cu because such a laminate structure comprises a barrier/adhesion layer structure that improves the integrity and reliability of the device (See ¶ 0031). As to claim 17, although Masuda discloses wherein at least one of the plurality of the transistor elements (101, 102) includes a switching element (channel, PN) controlled by a gate electrode (32) (See Fig. 1, Fig. 8), Masuda does not further disclose the semiconductor device further comprises a resistor element electrically connected to the gate electrode. However, Tee does disclose the semiconductor device further comprises a resistor element (metal silicide layer) electrically connected to the gate electrode (22) (See Fig. 8, Fig. 10, ¶ 0025, ¶ 0026, ¶ 0029) (Notes: the limitation “resistor element” is interpreted as an element presents a certain resistance). In view of the teaching of Tee, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Masuda to have the semiconductor device further comprises a resistor element electrically connected to the gate electrode because the resistor element serves as an interface layer and physical barrier connected to the gate electrode (See Fig. 10, ¶ 0025, ¶ 0026, ¶ 0029).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2016/0172437 A1 to Masuda (“Masuda”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2013/0089940 A1 to Arai et al. (“Arai”). The teaching of Masuda has been discussed above. As to claims 11 and 12, although Masuda discloses the first insulating film (31 right) (See Fig. 1, Fig. 8), Masuda does not further disclose wherein the first insulating film includes SiO2/SiN having a thickness of 1 μm or more. However, Arai does disclose wherein the first insulating film (22) includes SiO2/SiN (22) having a thickness of 1 μm or more (See Fig. 3, ¶ 0051). In view of the teaching of Arai, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Masuda to have wherein the first insulating film includes SiO2/SiN having a thickness of 1 μm or more because such a material is commonly applied as a gate insulating film and the thickness is sufficient to prevent leakage (See ¶ 0051).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2016/0172437 A1 to Masuda (“Masuda”) as applied to claim 1 above, and further in view of U.S. Patent No. 8,558,308 B1 to Blank et al. (“Blank”). The teaching of Masuda has been discussed above. As to claim 16, Masuda in view of Blank further discloses wherein an IGBT is formed in the SiC layer (21, 28) as at least one of the plurality of the transistor elements (101, 102), and the electrode (50/410) includes an emitter electrode (50/410) electrically connected to an emitter, which is a part of the IGBT through which the ON-current flows and a gate electrode (32/150) configured to control a switching operation of the IGBT (See Masuda Fig. 1, Fig. 8 and Blank Fig. 1, Fig. 2, Column 4, lines 11-26, Column 11, lines 29-36), where MOSFETs and IGBTs are known field effect transistors that define the function and surrounded by the outer peripheral region to obtain high reverse breakdown voltage (See Blank Column 4, lines 11-26, Column 11, lines 29-36).
Response to Arguments
Applicant's arguments filed on March 23, 2026 have been fully considered but they are not persuasive. Applicants argue “Referring to Fig. 1 of Masuda…Masuda fails to teach or suggest a structure in which the bottom portion of the surface insulating film is buried in a recess formed specifically in an n-type SiC layer.” This is not found persuasive because the rejection is in view of FIG. 8 of Masuda and as clearly seen in FIG. 8 and explicitly disclosed in [0080]…bottom surface 70a of peripheral region trench 70 is formed in drift layer 21, it is clear the recess is formed in the n-type SiC layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DAVID CHEN/Primary Examiner, Art Unit 2815
Prosecution Insights