DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Applicant’s election of the group I invention and species I, drawn to Figure 1 and claims 1-6 and 8-17 are acknowledged. Claim 7, drawn to an unelected species, is thus withdrawn from further examination. Claims 18-22, drawn to an unelected invention, are thus withdrawn from further examination. Claims 1-6 and 8-17 are examined herein.
Election/Restrictions
Applicant’s election without traverse of invention I, species I, claims 1-6 & 8-17 in the reply filed on 7/10/2026 is acknowledged.
Claim 7 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/10/2026.
Applicant’s election without traverse of claims 18-22 in the reply filed on 07/10/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/13/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 11, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Sadovnikov (US Patent Application Publication 2021/0210625A1) in view of Mahajan (US Patent No 11,749,672).
Regarding claim 1, Sadovnikov (US Patent Application Publication 2021/0210625A1) teaches A semiconductor device (transistor 100, Figure 1, paragraph 0019), comprising a semiconductor body (Figure 1, paragraphs 0020 + 0024, teaches a substrate, such as a semiconductor substrate or epitaxial layer that may be grown or deposited on the semiconductor…The semiconductor material, upon which the example transistor is fabricated, may be obtained from crystalline silicon grown from a seed, or the semiconductor material may also include epitaxial layers grown or deposited upon a semiconductor substrate) having a first surface and a second surface opposite to the first surface along a vertical direction; and a bipolar junction transistor (BJT) (Figure 1, paragraph 0020, teaches the transistor is a BJT) comprising: an emitter region (emitter region 114, Figure 1, paragraph 0020, teaches the transistor is a BJT that includes...an emitter region formed in a substrate) electrically connected to an emitter contact (emitter contact 132, Figure 1, paragraph 0023, teaches A respective metal layer is provided over each contact region to form...an emitter contact...Each contact may be coupled to a separate terminal of an IC chip that includes the transistor and/or to other circuitry integrated within the IC chip) at the first surface; a base region (base region 112, Figure 1, paragraph 0020, teaches the transistor is a BJT that includes...a base region...formed in a substrate) electrically connected to a base contact (base contact 128, Figure 1, paragraph 0023, teaches A respective metal layer is provided over each contact region to form...a base contact...Each contact may be coupled to a separate terminal of an IC chip that includes the transistor and/or to other circuitry integrated within the IC chip) at the first surface; a collector region (collector region 110, Figure 1, paragraph 0020, teaches the transistor is a BJT that includes a collector region...formed in a substrate) electrically connected to a collector contact (collector contact 126, Figure 1, paragraph 0023, teaches A respective metal layer is provided over each contact region to form a collector contact...Each contact may be coupled to a separate terminal of an IC chip that includes the transistor and/or to other circuitry integrated within the IC chip); a dielectric isolation structure (shallow trench isolation (STI) region 124, Figure 1, paragraph 0024, teaches the collector region may be fabricated within a well formed in the substrate, such as a semiconductor substrate or an epitaxial layer, and there may be shallow trench isolation (STI) regions to isolate the transistor from other devices) extending into the semiconductor body from the first surface; and a field plate structure (gate-type structure 102, Figure 1) including a field plate dielectric (Figure 1, paragraph 0023, teaches The gate contact is electrically isolated from the emitter contact and the base contact, such as by an insulating material (not shown)) and a field plate electrode (gate contact 130, Figure 1, paragraph 0023, teaches A respective metal layer is provided over each contact region to form...a gate contact) on the field plate dielectric, as claimed.
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Sadovnikov (US Patent Application Publication 2021/0210625A1) is silent to teach wherein the dielectric isolation structure includes a first sub-structure arranged, along a first lateral direction, between the emitter contact and the base contact, and wherein a first part of the field plate structure is arranged on the first surface of the semiconductor body and a second part of the field plate structure is arranged on the first sub-structure of the dielectric isolation structure.
In an analogous art, Mahajan (US Patent No 11,749,672) teaches wherein the dielectric isolation structure includes a first sub-structure (isolation regions 132, Figure 1, col 7, lines 25-27, teaches The second isolation region may be disposed between the emitter region and the base region) arranged, along a first lateral direction, between the emitter contact and the base contact, and wherein a first part of the field plate structure (Figure 1) is arranged on the first surface of the semiconductor body and a second part of the field plate structure is arranged on the first sub-structure of the dielectric isolation structure, as claimed.
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Sadovnikov (US Patent Application Publication 2021/0210625A1) with the teachings of Mahajan (US Patent No 11,749,672) by having the field plate structure partially on the dielectric isolation structure, thereby reducing device degradation caused by charge accumulation in the isolation structure and improving device reliability.
Regarding claim 2, Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) teach the semiconductor device of claim 1, as claimed. Mahajan (US Patent No 11,749,672) further teaches wherein the first sub-structure of the dielectric isolation structure is spaced from the emitter region along the first lateral direction (Figure 1), as claimed.
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Regarding claim 3, Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) teach the semiconductor device of claim 1, as claimed. Sadovnikov (US Patent Application Publication 2021/0210625A1) further teaches wherein the dielectric isolation structure is a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure (shallow trench isolation (STI) region 124, Figure 1, paragraph 0022, teaches A shallow trench isolation (STI) region may be formed between the collector contact region and the base contact region to provide electrical isolation), as claimed.
Regarding claim 4, Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) teach the semiconductor device of claim 1, as claimed. Sadovnikov (US Patent Application Publication 2021/0210625A1) further teaches wherein the base contact is arranged between the emitter contact and the collector contact along the first lateral direction (Figure 1), and wherein the collector region is electrically connected to the collector contact at the first surface (Figure 1), as claimed.
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Regarding claim 5, Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) teach the semiconductor device of claim 1, as claimed. Mahajan (US Patent No 11,749,672) further teaches wherein a lateral extent of the first part of the field plate structure along the first lateral direction has a value in a range from 30% to 90% of a lateral extent of the first sub-structure of the dielectric isolation structure along the first lateral direction at the first surface (Figure 1, MPEP 2144(II)(A) states, generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art.")).
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have optimized the teachings of Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) such that the ratio of the first part to the second part of the field plate structure is between 30% to 90%.
Regarding claim 6, Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) teach the semiconductor device of claim 1, as claimed. [2] further teaches wherein the first part of the field plate structure protrudes laterally over the first sub-structure of the dielectric isolation structure toward the emitter contact (Figure 1), as claimed.
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Regarding claim 10, Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) teach the semiconductor device of claim 1, as claimed. Sadovnikov (US Patent Application Publication 2021/0210625A1) further teaches wherein a vertical distance from a bottom side of the first sub-structure of the dielectric isolation structure to the first surface has a value in a range from 10 % to 30 % of a vertical distance from a bottom side of the base region to the first surface (Figure 1, MPEP 2144(II)(A) states, generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art.")).
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have optimized the teachings of Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) such that the ratio of the vertical distance of the base region and the vertical distance of the first sub-structure is between 10% to 30%.
Regarding claim 11, Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) teach the semiconductor device of claim 1, as claimed. Sadovnikov (US Patent Application Publication 2021/0210625A1) further teaches wherein the dielectric isolation structure includes a second sub-structure (shallow trench isolation (STI) region 124, Figure 1) arranged, along the first lateral direction, between the base contact and the collector contact (Figure 1, paragraph 0022, teaches A shallow trench isolation (STI) region may be formed between the collector contact region and the base contact region to provide electrical isolation), and wherein the field plate structure is omitted on the second sub-structure of the dielectric isolation structure (Figure 1), as claimed.
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Regarding claim 13, Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) teach the semiconductor device of claim 1, as claimed. Sadovnikov (US Patent Application Publication 2021/0210625A1) further teaches wherein the BJT is a pnp BJT (Figure 1, claim 5, teaches wherein the BJT is an NPN BJT or a PNP BJT) and the semiconductor body is a p-doped semiconductor substrate (Figure 1, paragraph 0020, teaches In some examples, the transistor is a PNP transistor, where the collector region and the emitter region are P-type semiconductors, and the base region is an N-type semiconductor. For a PNP transistor, the collector region and the emitter region can be fabricated by implanting acceptor dopants into a silicon semiconductor, and the base region can be fabricated by implanting donor dopants into the silicon semiconductor), as claimed.
Regarding claim 15, Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) teach the semiconductor device of claim 1, as claimed. Sadovnikov (US Patent Application Publication 2021/0210625A1) further teaches wherein in a top view, the field plate structure at least partially surrounds the emitter region (Figure 1, paragraph 0019, teaches The gate-type structure also surrounds the emitter region), as claimed.
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) in view of John (US Patent Application Publication 2024/024052A1).
Regarding claim 14, Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) teach the semiconductor device of claim 1, as claimed.
Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) are silent to teach wherein a doping concentration profile in the base region and a doping concentration profile in the collector region are configured for a collector-to-base breakdown voltage in a range from 5 V to 20 V.
In an analogous art John (US Patent Application Publication 2024/0204052A1) teaches wherein a doping concentration profile in the base region and a doping concentration profile in the collector region are configured for a collector-to-base breakdown voltage in a range from 5 V to 20 V (paragraph 0042, teaches the dopant concentration of the implanted region may be selected to achieve a desired collector-base junction breakdown voltage. MPEP 2144(II)(A) states, generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art.")).
Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have routinely optimized the teachings of Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) with the teachings of John (US Patent Application Publication 2024/0204052A1) thereby achieving a collector-to-base breakdown voltage between 5V and 20V.
Claim(s) 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US Patent Application Publication 2023/0127579A1) in view of Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672).
Regarding claim 16, Chen (US Patent Application Publication 2023/0127579A1) An integrated circuit (integrated circuit (IC) device 300, Figure 3), comprising: at least one of a voltage reference circuit and a temperature sensor circuit (paragraph 0023, teaches Various embodiments of the present disclosure will be described with respect to embodiments in a specific context, namely thermal sensors, or temperature sensors, which are widely used in various applications to sense a temperature. For example, thermal sensors can be used in integrated circuits, such as memory modules or central processing units (CPU), to monitor and facilitate control of the temperature of the integrated circuits to ensure the integrated circuits operate properly), wherein the at least one of the voltage reference circuit and the temperature sensor circuit include the BJT (paragraph 0003, teaches In some circuit designs, the thermal sensor may include bipolar junction transistors (BJTs) or resistive temperature sensors), as claimed.
Chen (US Patent Application Publication 2023/0127579A1) is silent to teach the semiconductor device of claim 1.
In analogous arts, Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) and teach the semiconductor device of claim 1 (transistor 100 + emitter region 114 + emitter contact 132 + collector region 110 + collector contact 126 + shallow trench isolation (STI) region 124 + gate contact 130 + gate-type structure 102 + base contact 128 + base region 112 + isolation regions 132 [Mahajan], Figure 1 [Sadovnikov] + Figure 1 [Mahajan], [Sadovnikov] paragraph 0019 + 0020 + 0023 + 0024, teaches a substrate, such as a semiconductor substrate or epitaxial layer that may be grown or deposited on the semiconductor…The semiconductor material, upon which the example transistor is fabricated, may be obtained from crystalline silicon grown from a seed, or the semiconductor material may also include epitaxial layers grown or deposited upon a semiconductor substrate…the transistor is a BJT…the transistor is a BJT that includes...an emitter region formed in a substrate…A respective metal layer is provided over each contact region to form...an emitter contact...Each contact may be coupled to a separate terminal of an IC chip that includes the transistor and/or to other circuitry integrated within the IC chip…the transistor is a BJT that includes...a base region...formed in a substrate…A respective metal layer is provided over each contact region to form...a base contact...Each contact may be coupled to a separate terminal of an IC chip that includes the transistor and/or to other circuitry integrated within the IC chip…the transistor is a BJT that includes a collector region...formed in a substrate…A respective metal layer is provided over each contact region to form a collector contact...Each contact may be coupled to a separate terminal of an IC chip that includes the transistor and/or to other circuitry integrated within the IC chip…the collector region may be fabricated within a well formed in the substrate, such as a semiconductor substrate or an epitaxial layer, and there may be shallow trench isolation (STI) regions to isolate the transistor from other devices…A respective metal layer is provided over each contact region to form...a gate contact; [Mahajan] col 7, lines 25-27, teaches The second isolation region may be disposed between the emitter region and the base region), as claimed.
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Chen (US Patent Application Publication 2023/0127579A1) to incorporate the semiconductor device of Sadovnikov (US Patent Application Publication 2021/0210625A1) and Mahajan (US Patent No 11,749,672) thereby having an IC configured with the claimed BJT structure.
Regarding claim 17, Chen (US Patent Application Publication 2023/0127579A1), Sadovnikov (US Patent Application Publication 2021/0210625A1), and Mahajan (US Patent No 11,749,672) teach the integrated circuit of claim 16, as claimed. Chen (US Patent Application Publication 2023/0127579A1) further teaches further comprising a CMOS circuit block (Figure 3, paragraph 0039, teaches In some embodiments, first standard cells and second standard cells may be logic gate cells. In some embodiments, a logic gate cell includes an AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX, Flip-flop, BUFF, Latch, delay, clock cells, or the like. In some embodiments, standard cells may be memory cells. In some embodiments, a memory cell includes a static random access memory (SRAM), a dynamic RAM (DRAM), a resistive RAM (RRAM), a magnetoresistive RAM (MRAM) read only memory (ROM), or the like. In some embodiments, standard cells may include one or more active or passive elements. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), FinFETs, planar MOS transistors with raised source/drain, or the like. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, resistors, or the like. The first standard cells and the second standard cells may include other features not shown for ease of illustration), as claimed.
Allowable Subject Matter
Claims 8-9, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The lateral extent of the second part of the field plate structure along the first lateral direction being smaller than a lateral extent of the first sub-structure of the dielectric isolation structure along the first lateral direction at the first surface in claim 8.
The field plate electrode being electrically coupled to the emitter contact in claim 9.
The lateral extent of the first sub-structure of the dielectric isolation structure along the first lateral direction at the first surface being larger than a lateral extent of the second sub-structure of the dielectric isolation structure along the first lateral direction at the first surface in claim 12.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM M MOHAMED-ALY whose telephone number is (571)270-0312. The examiner can normally be reached Monday – Friday 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREEM M MOHAMED-ALY/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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