DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al (US 2022/0238065 A1).
Regarding claim 1, Liu discloses a display device comprising: pixels [e.g., Fig. 6: 100; Paragraph 140: pixels],
wherein each of the pixels includes a first transistor [e.g., Fig. 3: T3, T9] and a bypass transistor [e.g., Fig. 3: T8],
wherein the first transistor includes a first sub-driving transistor [e.g., Fig. 3: T3] and a second sub-driving transistor [e.g., Fig. 3: T9],
wherein the first sub-driving transistor has
a gate electrode [e.g., Fig. 3: T3 gate] connected to a first node [e.g., Fig. 3: Vg node],
a first electrode [e.g., Fig. 3: T3 source] connected to a second node [e.g., Fig. 3: T3-T4 node], and
a second electrode [e.g., Fig. 3: T3 drain] connected to a third node [e.g., Fig. 3: T3-T6 node],
wherein the second sub-driving transistor has
a gate electrode [e.g., Fig. 3: T9 gate] connected to the first node,
a first electrode [e.g., Fig. 3: T9 source] connected to the third node, and
a second electrode [e.g., Fig. 3: T9 drain] connected to a fourth node [e.g., Fig. 3: C1-T1 node], and
wherein the bypass transistor and one of the first sub-driving transistor and the second sub-driving transistor are connected in parallel [e.g., see Fig. 3; Paragraph 131: T3 and T8 are connected in parallel] (e.g., see Paragraphs 77-141).
Regarding claim 2, Liu discloses the bypass transistor is turned off [e.g., Figs. 4-5: t1; Paragraph 130: T8 turned off] in a first mode [e.g., Fig. 5; Fig. 7: G=0; Paragraph 132: 1st period of time including low-grayscale display] and turned on [e.g., Figs. 4-5: t3; Paragraph 131: T8 turned on] in a second mode [e.g., Fig. 4; Fig. 7: G=255; Paragraph 127: 2nd period of time including high-grayscale display] (e.g., see Paragraphs 77-141).
Regarding claim 3, Liu discloses for the same input image [e.g., Paragraph 4: image; Fig. 7], the pixels output an image with a first luminance [e.g., Fig. 5; Fig. 7: G=0; Paragraph 132: low-grayscale display] in the first mode and output an image with a second luminance [e.g., Fig. 4; Fig. 7: G=255; Paragraph 127: high-grayscale display] in the second mode, and wherein the second luminance is greater than the first luminance (e.g., see Paragraphs 77-141).
Regarding claim 4, Liu discloses a gate electrode [e.g., Fig. 3: T8 gate] of the bypass transistor is connected to a bypass line [e.g., Fig. 3: DI], and
wherein the bypass line is commonly connected to the pixels [e.g., Paragraph 141: the pixel driving circuits 10 of pixels in a same column are electrically coupled to a same first data line].
Regarding claim 14, Liu discloses the bypass transistor and the first sub-driving transistor are connected in parallel [e.g., see Fig. 3; Paragraph 131: T3 and T8 are connected in parallel].
Regarding claim 15, Liu discloses each of the pixels further includes:
a second transistor [e.g., Fig. 3: T2] having
a gate electrode [e.g., Fig. 3: T2 gate] connected to a first scan line [e.g., Fig. 3: GA],
a first electrode [e.g., Fig. 3: T2 source] connected to a data line [e.g., Fig. 3: DI], and
a second electrode [e.g., Fig. 3: T2 drain] connected to the second node;
a third transistor [e.g., Fig. 3: T5] having
a gate electrode [e.g., Fig. 3: T5 gate] connected to the first scan line,
a first electrode [e.g., Fig. 3: T5 source] connected to the first node, and
a second electrode [e.g., Fig. 3: T5 drain] connected to the fourth node;
a fourth transistor [e.g., Fig. 3: T1] having
a gate electrode [e.g., Fig. 3: T1 gate] connected to a second scan line [e.g., Fig. 3: R1],
a first electrode [e.g., Fig. 3: T1 source] connected to the first node, and
a second electrode [e.g., Fig. 3: T1 drain] receiving a first initialization voltage [e.g., Fig. 3: F1];
a fifth transistor [e.g., Fig. 3: T4] having
a gate electrode [e.g., Fig. 3: T4 gate] connected to a third scan line [e.g., Fig. 3: E1],
a first electrode [e.g., Fig. 3: T4 source] receiving a first power source voltage [e.g., Fig. 3: VDD], and
a second electrode [e.g., Fig. 3: T4 drain] connected to the second node;
a sixth transistor [e.g., Fig. 3: T6] having
a gate electrode [e.g., Fig. 3: T6 gate] connected to the third scan line,
a first electrode [e.g., Fig. 3: T6 source] connected to the fourth node, and
a second electrode [e.g., Fig. 3: T7] connected to a fifth node [e.g., Fig. 3: T6-O1 node]; and
a seventh transistor [e.g., Fig. 3: T10 gate] having
a gate electrode [e.g., Fig. 3: T10 gate] connected to the first scan line,
a first electrode [e.g., Fig. 3: T10 source] receiving a second initialization voltage [e.g., Fig. 3: DT], and
a second electrode [e.g., Fig. 3: T10 drain] connected to the fifth node (e.g., see Paragraphs 77-141).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (US 2022/0238065 A1).
Regarding claim 13, Liu discloses varying transistor width-to-length ratios (e.g., see Paragraphs 107-111).
Liu doesn’t appear to expressly disclose a width of a first channel of the first sub-driving transistor is smaller than a width of a second channel of the second sub-driving transistor, and wherein a length of the first channel is longer than a length of the second channel.
However, the width of the first channel can only be either smaller than, equal to, or larger than the width of the second channel.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing, because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp (i.e., making the width of the first channel either smaller than, equal to, or larger than the width of the second channel). If this leads to the anticipated success, it is likely the product is not of innovation but of ordinary skill and common sense. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Moreover, the length of the first channel only be either shorter than, equal to, or longer than the length of the second channel.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing, because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp (i.e., making the length of the first channel either shorter than, equal to, or longer than the length of the second channel). If this leads to the anticipated success, it is likely the product is not of innovation but of ordinary skill and common sense. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Election/Restrictions
Applicant’s election without traverse of Species 1, 5 and 12 in the reply filed on 27 January 2026 is acknowledged.
Claims 5-12 and 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to at least a nonelected species/invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 27 January 2026.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The documents listed on the attached 'Notice of References Cited' are cited to further evidence the state of the art pertaining to display devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached on Monday - Friday (7:30AM - 4PM). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Jeff Piziali/
Primary Examiner, Art Unit 2628
6 February 2026