DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102 / 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 4 and 14 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Kanda et al (US 2015/0061537 A1);
or, in the alternative, under 35 U.S.C. 103 as obvious over Kanda et al (US 2015/0061537 A1) in view of Kim et al (US 2021/0036079 A1);
or, in the alternative, under 35 U.S.C. 103 as obvious over Kim et al (US 2021/0036079 A1) in view of Kanda et al (US 2015/0061537 A1).
Regarding claim 1, Kanda discloses a display device [see Paragraphs 5, 53, 96] comprising: pixels [Fig. 1: 1; see Paragraph 115],
wherein each of the pixels includes a first transistor [Fig. 11: 11, 13] and a bypass transistor [Fig. 11: 18],
wherein the first transistor includes a first sub-driving transistor [Fig. 11: 11] and a second sub-driving transistor [Fig. 11: 13],
wherein the first sub-driving transistor has a gate electrode connected to a first node [Fig. 11: 11 gate at 14/31 junction], a first electrode connected to a second node [Fig. 11: 11/12 junction], and a second electrode connected to a third node [Fig. 11: 13/11 junction],
wherein the second sub-driving transistor has a gate electrode connected to the first node, a first electrode connected to the third node, and a second electrode connected to a fourth node [Fig. 11: 17/13 junction], and
wherein the bypass transistor and one of the first sub-driving transistor and the second sub-driving transistor are connected in parallel [see Fig. 11, Paragraph 92], and
wherein the first sub-driving transistor and the second sub-driving transistor are connected in series [see Fig. 11, Paragraph 90] (see Figs. 1, 2, 11-17; Paragraphs 49-114).
Alternatively (1): Should it be shown Kanda discloses the second sub-driving transistor has a gate electrode connected to the first node with insufficient specificity:
Kim (‘079) discloses a display device [Fig. 1: 1] comprising: pixels [Fig. 1: PXL],
wherein each of the pixels includes a first transistor [Figs. 2, 3: T1],
wherein the first transistor includes a first sub-driving transistor [Figs. 2, 3: T1_1] and a second sub-driving transistor [Figs. 2, 3: T1_2],
wherein the first sub-driving transistor has a gate electrode connected to a first node [Figs. 2, 3: N1], a first electrode connected to a second node [Figs. 2, 3: T5/T1_1 junction], and a second electrode connected to a third node [Figs. 2, 3: T1_1/T1_2 junction],
wherein the second sub-driving transistor has a gate electrode [Figs. 2, 3: T1_2 gate at N1] connected to the first node, a first electrode connected to the third node, and a second electrode connected to a fourth node [Figs. 2, 3: T1_2/T6 junction], and
wherein the first sub-driving transistor and the second sub-driving transistor are connected in series [Figs. 2, 3; see Paragraphs 7, 74] (see Figs. 1- 3; Paragraphs 42-101).
Kim (‘079) teaches configuring a pixel's drive element as a first transistor T1 including first and second driving transistors T1_1 and T1_2 connected in series with each other, with both gate electrodes connected to the same first node N1, the composite transistor controlling the driving current in response to the voltage of that single node (Paragraphs 73—74; Figs. 2—3).
Kim (‘079) states the benefits expressly: the area occupied by the first transistor in each pixel region is reduced while the driving range is sufficiently secured, whereby "an image quality of the display device 1 may be improved while a limited pixel region may be efficiently utilized," including in high-resolution display devices (Paragraphs 75—76); the segments may further be individually configured — for example, with different channel lengths — to tune the driving range (Paragraph 77).
Kanda and Kim (‘079) are analogous art, because they are from the shared inventive field of light-emitting diode display devices.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to configure Kanda's series-connected correction transistor 13 and driving transistor 11 — already matched devices of equal threshold voltage jointly disposed in the first-current path (Paragraphs 90, 94) — as a common-gate pair of sub-driving transistors of a single first transistor in accordance with Kim (‘079), with both gates connected to the pixel's drive-control storage node, while retaining Kanda's bypass transistor 18 across one of the pair and its commonly connected bypass line N (Paragraphs 92, 53).
The rationale is the use of a known technique to improve a similar device in the same way: Kim (‘079)'s common-gate series configuration and its stated area, driving-range, image-quality, and high-resolution benefits (Paragraphs 75—76) apply directly to Kanda's pixel; equivalently, the combination is a simple substitution of one known series drive-pair configuration (common-gate, Kim (‘079)) for another (separately gated, Kanda) with predictable results — the driving current remains established at a single storage node, and the bypass still selectably diverts the current around one segment (Kanda, Paragraphs 8—9, 92).
The test for obviousness is not whether Kanda's circuit may be bodily incorporated into Kim (‘079)'s, but what the combined teachings would have suggested to one of ordinary skill (In re Keller; In re Mouttet); those teachings suggest precisely the claimed arrangement — a common-gate series pair with a bypass in parallel with one member — operating per Kim (‘079)'s ordinary programming of the common gate node while providing Kanda's second-current bypass function.
A reasonable expectation of success follows: both references employ conventional thin-film-transistor OLED pixel integration, and Kanda demonstrates the bypass operating across a series drive-path transistor in a complete working pixel (Paragraphs 90—98).
To the extent the references employ opposite channel types (Kim (‘079)'s transistors are gate-on at a low level, Paragraph 80; Kanda's are N-channel, Paragraph 94), implementation involves only routine selection of channel type and control-signal polarity.
Alternatively (2): Kim (‘079) does not disclose a bypass transistor connected in parallel with one of the first and second sub-driving transistors.
Kanda teaches a pixel driving circuit in which a correction transistor 13 and a driving transistor 11 are connected in series in the path of the first current (Paragraph 90), the two being matched devices whose "threshold voltages may be equal to each other" (Paragraph 94); a bypass transistor 18 "connected between a drain and a source of the driving transistor 11" — in parallel with exactly one transistor of the series pair — serving as "a switch for second current as a means for regulating the second current" (Paragraph 92), whereby the second current "pass[es] through the source of the driving transistor without passing through the driving transistor" (Paragraph 8) and is blocked while the first current flows (Paragraph 9); and the bypass gate driven from line N, connected in common to the driving circuits of the pixels of a row and operated simultaneously for all rows (Paragraphs 53, 92, 96).
It would have been obvious to one of ordinary skill in the art at the time of filing to provide, in Kim (‘079)'s pixel, a bypass transistor connected in parallel with one of the sub-driving transistors T1_1 and T1_2 (e.g., across T1_1), with its gate connected to a commonly connected control line, as taught by Kanda.
Kanda teaches this precise technique — a bypass switch across one member of a matched, series-connected drive pair — for selectably establishing a second current configuration in which the current does not pass through the bypassed transistor (Paragraphs 8—9, 92).
Applied to Kim (‘079)'s pair, the technique yields the predictable result that, when the bypass conducts, the driving current flows through the remaining sub-driving transistor alone, selectably altering the effective conduction characteristics of the composite first transistor — the very parameter Kim (‘079) ties to the driving range through the segments' dimensions (Paragraphs 75—77).
This is the application of a known technique to a known device ready for improvement, and the combination of prior-art elements according to known methods, yielding predictable results.
A reasonable expectation of success follows: both references employ conventional thin-film-transistor OLED pixel integration, and Kanda demonstrates the bypass operating across a series drive-path transistor in a complete working pixel (Paragraphs 90—98). To the extent the references employ opposite channel types (Kim (‘079)'s transistors are gate-on at a low level, Paragraph 80; Kanda's are N-channel, Paragraph 94), implementation involves only routine selection of channel type and control-signal polarity.
Contemporaneous art further evidences the recognized demand for pixel drive strength selectable between operating modes (Kim et al (US 2024/0177668 A1), Paragraphs 17, 48—51; Liu (US 2022/0238065 A1), Paragraphs 111, 131) — cited as evidence of the state of the art, not as part of the combination for claim 1.
Regarding claim 2, Kanda discloses the bypass transistor is turned off in a first mode [see Fig. 13, Paragraphs 96—98: bypass transistor 18 is turned off] and turned on in a second mode [Fig. 16; see Paragraphs 105, 108: the bypass transistor 18 is turned on].
Regarding claim 4, Kanda discloses a gate electrode of the bypass transistor is connected to a bypass line [Fig. 11: N; see Paragraph 92], and wherein the bypass line is commonly connected to the pixels [see Paragraphs 53, 96].
Regarding claim 14, Kanda discloses the bypass transistor and the first sub-driving transistor are connected in parallel [see Fig. 11; Paragraph 92].
Claim 3 is rejected under 35 U.S.C. 103 as obvious over Kanda et al (US 2015/0061537 A1) in view of Kim et al (US 2024/0177668 A1);
or, in the alternative, under 35 U.S.C. 103 as obvious over Kanda et al (US 2015/0061537 A1) in view of Kim et al (US 2021/0036079 A1) as applied to claim 2 above, and further in view of Kim et al (US 2024/0177668 A1);
or, in the alternative, under 35 U.S.C. 103 as obvious over Kim et al (US 2021/0036079 A1) in view of Kanda et al (US 2015/0061537 A1) as applied to claim 2 above, and further in view of Kim et al (US 2024/0177668 A1).
Regarding claim 3, Kanda and Kim (‘079) don’t appear to expressly disclose for the same input image, the pixels output an image with a first luminance in the first mode and output an image with a second luminance in the second mode, and wherein the second luminance is greater than the first luminance.
However, Kim (‘668) discloses for the same input image, the pixels output an image with a first luminance in the first mode [see Paragraphs 81, 111: "during the normal mode driving, only the first driving transistor DTI... can be driven"; the second driver's current 1b "may not be output"] and output an image with a second luminance in the second mode [see Paragraph 82: "during the high luminance mode driving, both of the first driver PDI and the second driver PD2 can be driven at the same time"], and wherein the second luminance is greater than the first luminance [see Paragraphs 17, 50: luminance "improved without increasing an output range of the data voltage"; the high luminance mode used "when an external environment of the display device 100 is very bright"].
Kanda, Kim (‘079) and Kim (‘668) are analogous art, because they are from the shared inventive field of light-emitting diode display devices.
It would have been obvious to one of ordinary skill in the art at the time of filing to operate the combination's bypass transistor according to Kim (‘668)'s mode scheme — off in a normal mode, on in a high luminance mode — because Kim (‘668) articulates both the demand and the constraints: high luminance is needed when outdoor visibility is degraded (Paragraph 50), normal-mode operation should be retained otherwise to save power (Paragraph 51), and the boost should come without increasing the data-voltage output range (Paragraph 17).
In the combined pixel, turning the bypass on in the second mode diverts the current around one sub-driving transistor so that the same data produces a greater driving current and hence greater luminance — accomplishing Kim (‘668)'s stated objective through the combination's own mechanism.
This is the application of a known technique (mode-gating an added current capability) to a device ready for its benefit, with predictable results; a reasonable expectation of success follows because the bypass gate line is already commonly connected to the pixels (Kanda, Paragraph 53) and mode-dependent control signals are conventionally distributed (Kim (‘668), Paragraphs 48—51).
Claim 13 is rejected under 35 U.S.C. 103 as obvious over Kanda et al (US 2015/0061537 A1);
or, in the alternative, under 35 U.S.C. 103 as obvious over Kanda et al (US 2015/0061537 A1) in view of Kim et al (US 2021/0036079 A1);
or, in the alternative, under 35 U.S.C. 103 as obvious over Kim et al (US 2021/0036079 A1) in view of Kanda et al (US 2015/0061537 A1).
Regarding claim 13, Kim (‘079) discloses a width of a first channel of the first sub-driving transistor is different than a width of a second channel of the second sub-driving transistor [see Paragraph 100], and wherein a length of the first channel is longer than a length of the second channel [see Paragraph 77].
Kim (‘079) expressly discloses the recited channel-length relationship (Paragraph 77: the first driving transistor's channel region "may be greater (e.g., longer) than" the second's, to secure the driving range).
It would have been obvious to one of ordinary skill in the art at the time of filing to make the first channel's width smaller than the second's.
The relative width presents a finite number of identified, predictable solutions — smaller than, equal to, or greater than — and channel width is an art-recognized result-effective variable determining drive-current amplitude.
It would have been obvious to one of ordinary skill in the art at the time of filing, because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp (i.e., making a width of a first channel of the first sub-driving transistor smaller than, equal to, or larger than a width of a second channel of the second sub-driving transistor). If this leads to the anticipated success, it is likely the product is not of innovation but of ordinary skill and common sense. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Moreover, Liu (US 2022/0238065 A1 – cited merely in an evidential capacity) expresses the driving current directly in terms of the channel's width-to-length ratio (Paragraph 111: K = (W/L)xCxµ) and teaches that, of two driving transistors, the one supplying the larger current is given the larger width-to-length ratio (Paragraphs 12, 107, 111).
In the claimed combination the second sub-driving transistor alone conducts the boosted second-mode current while the first is bypassed; selecting the smaller width for the first channel — alongside the longer first-channel length Kim (‘079) itself teaches (Paragraph 77) — is ordinary optimization of recognized result-effective variables, and the claimed selections together yield precisely the relationship Liu prescribes for such a pair: a first driving transistor whose width-to-length ratio is smaller than the second's (Paragraph 12).
The selection was obvious to try, with predictable results and a reasonable expectation of success through routine mask-level dimensioning.
Claim 15 is rejected under 35 U.S.C. 103 as obvious over Kanda et al (US 2015/0061537 A1) in view of Kim et al (US 2021/0036079 A1);
or, in the alternative, under 35 U.S.C. 103 as obvious over Kim et al (US 2021/0036079 A1) in view of Kanda et al (US 2015/0061537 A1);
or, in the alternative, under 35 U.S.C. 103 as obvious over Kanda et al (US 2015/0061537 A1) in view of Kim et al (US 2021/0036079 A1) as applied to claim 14 above, and further in view of Lee et al (US 2022/0158051 A1);
or, in the alternative, under 35 U.S.C. 103 as obvious over Kim et al (US 2021/0036079 A1) in view of Kanda et al (US 2015/0061537 A1) as applied to claim 14 above, and further in view of Lee et al (US 2022/0158051 A1).
Regarding claim 15, Kim (‘079) discloses each of the pixels further includes:
a second transistor [Figs. 2, 3: T2] having a gate electrode connected to a first scan line [Figs. 2, 3: Si], a first electrode connected to a data line [Figs. 2, 3: Dj], and a second electrode connected to the second node [see Figs. 2, 3; Paragraph 79];
a third transistor [Figs. 2, 3: T3] having a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to the fourth node [see Figs. 2, 3; Paragraph 81];
a fourth transistor [Figs. 2, 3: T4] having a gate electrode connected to a second scan line [Figs. 2, 3: CL1i; see Paragraph 84], a first electrode connected to the first node, and a second electrode receiving a first initialization voltage [Figs. 2, 3: Vint; see Paragraph 83];
a fifth transistor [Figs. 2, 3: T5] having a gate electrode connected to a third scan line [Figs. 2, 3: Ei], a first electrode receiving a first power source voltage [Figs. 2, 3: ELVDD], and a second electrode connected to the second node [see Paragraph 90];
a sixth transistor [Figs. 2, 3: T6] having a gate electrode connected to the third scan line, a first electrode connected to the fourth node, and a second electrode connected to a fifth node [Figs. 2, 3: T6/T7/EL junction; see Paragraph 91]; and
a seventh transistor [Figs. 2, 3: T7] having a gate electrode connected to the first scan line [see Paragraph 95: the second control line CL2i "may be a current scan line (e.g., the scan line Si)"], a first electrode receiving a second initialization voltage [Figs. 2, 3: Vint; see Paragraph 83], and a second electrode connected to the fifth node [see Paragraph 94].
Should it be shown Kim (‘079) discloses a second initialization voltage with insufficient specificity:
Lee discloses each of the pixels further includes:
a second transistor [Fig. 2: T2] having a gate electrode connected to a first scan line [Fig. 2: 151], a first electrode connected to a data line [Fig. 2: 171], and a second electrode connected to the second node [Fig. 2: D5];
a third transistor [Fig. 2: T3] having a gate electrode connected to the first scan line, a first electrode connected to the first node [Fig. 2: T1 gate], and a second electrode connected to the fourth node [Fig. 2: D1];
a fourth transistor [Fig. 2: T4] having a gate electrode connected to a second scan line [Fig. 2: 153], a first electrode connected to the first node, and a second electrode receiving a first initialization voltage [Fig. 2: Vint];
a fifth transistor [Fig. 2: T5] having a gate electrode connected to a third scan line [Fig. 2: 155], a first electrode receiving a first power source voltage [Fig. 2: ELVDD], and a second electrode connected to the second node [Fig. 2: S1];
a sixth transistor [Fig. 2: T6] having a gate electrode connected to the third scan line, a first electrode connected to the fourth node, and a second electrode connected to a fifth node [Fig. 2: LED anode]; and
a seventh transistor [Fig. 2: T7] having a gate electrode connected to the first scan line, a first electrode receiving a second initialization voltage [Fig. 2: T7, VAINT, 128; see Paragraph 87: the seventh transistor T7 initializes the anode, its electrode "electrically connected to the second initialization voltage line 128," whereby "the second initialization voltage VAINT may be applied to the anode"; Paragraph 79: line 127 transmits the first initialization voltage VINT and line 128 transmits the second initialization voltage VAINT, the applied voltages "may be constant"], and a second electrode connected to the fifth node.
Kanda, Kim (‘079) and Lee are analogous art, because they are from the shared inventive field of light-emitting diode display devices.
It would have been obvious to one of ordinary skill in the art at the time of filing to supply the anode-initializing seventh transistor of the combination from a dedicated second initialization voltage as taught by Lee, so that the anode reset level is established by its own constant supply (Paragraph 79) independently of the gate-initialization voltage — a simple substitution of a known dual-initialization arrangement for the shared single voltage of Kim (‘079) (Paragraph 94), with predictable results.
Dual initialization voltages are further evidenced as conventional by Kanda's own first and second initialization voltages Vinit1 and Vinit2 (Kanda, Paragraphs 105-106).
A reasonable expectation of success is manifest: one additional constant voltage line, routed as Lee shows (Fig. 2; Paragraphs 67, 79), including in mesh form (Paragraph 67).
Response to Arguments
Applicant's arguments filed on 7 May 2026 have been fully considered but they are not persuasive.
Applicant's arguments with respect to claims 1-4 and 13-15 have been considered but are moot in view of any new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated any new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached on Monday - Friday (7:30AM - 4PM). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
13 July 2026
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