Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7, 9-10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kobata (US20210237224A1) in view of Barkam (US11731231B2).
Regarding claim 1, Kobata discloses a system for manufacturing a semiconductor device, (see Abstract) the system comprising: a processor coupled to a non-transitory computer-readable medium storing computer-executable instructions; (see ¶[0078]-[0080]: operation controller 10 coupled to a hard disk drive or solid state drive storing computer-executable instructions)
a stage including piezoelectric elements and electrically coupled to the processor, (see FIG. 29: carrier 45 including piezoelectric elements 47 and electrically coupled to operation controller 10)
wherein the piezoelectric elements are configured to collect [data]; (piezoelectric elements 47 are configured to data on reaction forces; see ¶[0139])
and a flattening apparatus electrically coupled to the processor and configured to hold a first wafer, (see ¶[0222]: the polishing apparatus shown in FIG. 29 is electrically coupled to operation controller 10 and configured to hold workpiece W)
wherein the processor executes the computer-executable instructions to cause the flattening apparatus to flatten the first surface of the first wafer based on the data (see ¶[0222]: operation controller 10 executes instruction values to cause the polishing apparatus to flatten the top surface of workpiece W based on the data).
Kobata does not teach that the data is of a first surface of the first wafer supported by the stage.
However, Barkam (US11731231B2), in the same or similar field of endeavor related to wafer manufacturing systems incorporating piezoelectric sensors, teaches that a stage supporting a first wafer (polishing pad 102 for supporting wafer 112; see Barkam FIG. 1 and Col. 3, Lines 28-48) is configured to sense data of a first surface of the first wafer (polishing pad 102 is configured to sense surface topography of a first surface of the wafer 112; see Barkam Col. 4, Lines 7-29),
wherein the flattening apparatus flattens the first surface of the first wafer based on the data of a first surface of the first wafer supported by the stage (polishing pad 102 flattens a surface of wafer 112 based on the topography data of wafer 112 supported by the polishing pad 102; see Barkam Col. 8, Lines 29-Col. 9, Line 42).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the piezoelectric elements of Kobata to sense data of a first surface of the first wafer, as taught by Barkam. One would have been motivated to make such a modification to “reduce the area and degree of over-polished and under-polished regions of the surface of wafer 112 during a CMP process” (Barkam Col. 9, Line 51-Col. 10, Line 18).
Regarding claim 2, the rejection of claim 1 is incorporated in this rejection. Kobata, as modified, further teaches that the piezoelectric elements are disposed on a top surface of the stage and configured to be in contact with the first surface of the first wafer when the first wafer is placed on the stage (see Kobata FIG. 29: carrier 45 includes piezoelectric elements 47 disposed on a top surface of carrier 45 and in contact with the first surface of workpiece W when workpiece W is placed on carrier 45).
Regarding claim 5, the rejection of claim 1 is incorporated in this rejection. Kobata, as modified, further teaches that the flattening apparatus is configured to perform a physical polishing process (the polishing apparatus performs a physical polishing process; see Kobata ¶[0212]-[0213]).
Regarding claim 6, the rejection of claim 1 is incorporated in this rejection. Kobata, as modified, further teaches that the flattening apparatus comprises: a polishing head; and a controller coupled to the polishing head, (the polishing apparatus in FIG. 29 comprises a polishing head 7 and operation controller 10 coupled to polishing head 7)
wherein the controller is configured to control the polishing head to apply a first pressure to a first location of the first wafer in response to the data collected from the first surface of the first wafer (see Kobata FIG. 4 and ¶[0213]-[0214]: operation controller 10 is configured to control the piezoelectric elements 47 on polishing head 7 to apply a first pressure to a first location of workpiece W in response to the sensed data).
Regarding claim 7, the rejection of claim 6 is incorporated in this rejection. Kobata, in another embodiment, teaches that the controller is configured to control the polishing head to apply a second pressure different from the first pressure to a second location different from the first location of the first wafer, in response to the data collected from the first surface of the first wafer (see FIG. 5 and ¶[0102]-[0104]: operation controller 10 controls polishing head 7 to apply different pressing forces to a plurality of regions of workpiece W in response to the sensed data from the first surface of workpiece W—resulting from the modification discussed in the rejection of claim 1 above).
Regarding claim 9, the rejection of claim 6 is incorporated in this rejection. Kobata, as modified, further teaches that the flattening apparatus further comprises a rotatable supporting element configured to hold the first wafer (the polishing apparatus in FIG. 29 further comprises rotatable head shaft 18 configured to hold workpiece W).
Regarding claim 10, the rejection of claim 6 is incorporated in this rejection. Kobata, as modified, further teaches that the polishing head is rotatable (polishing head 7 is rotatable; see FIG. 29).
Regarding claim 12, the rejection of claim 1 is incorporated in this rejection. In light of ¶[0003] of the specification of the instant application, the “back side” of a wafer is understood to be the side of the wafer with “foreign objects/particles, film residue, uneven film, or other defects” resulting from “processes, such as etching, deposition, or diffusion.” Kobata teaches that the film on wafer W is formed by a deposition process and polished with a polishing pad (see Kobata ¶[0002] and [0004]-[0005]). Thus, Kobata, as modified, further teaches that the first surface of the wafer is a backside surface (the top surface of workpiece W in FIG. 29, being polished by polishing pad 2, is a surface with an uneven film formed by a deposition process).
Regarding claim 13, the rejection of claim 1 is incorporated in this rejection. Kobata, as modified, further teaches the flattening apparatus is configured to remove foreign objects from the first surface of the first wafer, wherein the foreign objects are introduced by an etching process, a deposition process, or a diffusion process that has performed on the wafer (see Kobata ¶[0005]: extra film thickness is introduced by deposition processes performed on wafer W).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kobata (US 20210237224 A1) in view of Barkam (US 11731231 B2), further in view of GanapathiSubramanian (US 7307697 B2).
Regarding claim 3, the rejection of claim 1 is incorporated in this rejection. Kobata, as modified, does not teach that each of the piezoelectric elements has an area in a range of 1 mm2 to 100 mm2 in a top view.
However, GanapathiSubramanian, in the same or similar field of endeavor related to wafer manufacturing systems involving piezoelectric elements, teaches that each of the piezoelectric elements has an area in a range of 1 mm2 to 100 mm2 in a top view (each piezo pin 81 has a square cross-sectional area of 3 mm2; see Col. 4, Line 57—Col. 5, Line 25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the piezoelectric elements of Kobata, as modified, to have an area in the range of 1 mm2 to 100 mm2 in a top view, as taught by GanapathiSubramanian. One would have been motivated to make such a modification to provide high precision and minimize error of the sensors (Col. 4, Line 57—Col. 5, Line 25).
Regarding claim 4, the rejection of claim 1 is incorporated in this rejection. Kobata, as modified, does not teach that the piezoelectric elements are configured to sense a deformation on the first wafer in a nanometer scale.
However, GanapathiSubramanian teaches that the piezoelectric elements are configured to sense a deformation on the first wafer in a nanometer scale (“sub-100 nanometer variations in substrate surface topology”; see Col. 5, Lines 56-65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the piezoelectric elements of Kobata, as modified, to sense a deformation on the first wafer in a nanometer scale to provide smooth and continuous data across the surface of the wafer (Col. 5, Lines 56-65).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kobata (US 20210237224 A1) in view of Barkam (US 11731231 B2), further in view of Yasuda (US20180236630A1).
Regarding claim 8, the rejection of claim 6 is incorporated in this rejection. Kobata, as modified, does not teach that the polishing head is movable in three-dimension.
However, Yasuda, in the same or similar field of endeavor related to wafer polishing devices, teaches a polishing head movable in three-dimension (see Yasuda FIG. 1: holding arm 600, which holds the polishing head 500, is movable in the x, y, and z directions; see also ¶[0115]-[0116]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the polishing head of Kobata, as modified, to be movable in three-dimension, as taught by Yasuda. One would have been motivated to make such a modification to provide “the effect of homogenizing the shapes of the processed marks can be provided” (¶[0116]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kobata (US 20210237224 A1) in view of Barkam (US 11731231 B2), further in view of Shibue (US 20220219283 A1).
Regarding claim 11, the rejection of claim 1 is incorporated in this rejection. Kobata, as modified, does not explicitly teach that the flattening apparatus is configured to flatten the first wafer before an exposure process to be conducted on the first wafer.
However, Shibue, in the same or similar field of endeavor related to systems for polishing wafers incorporating piezoelectric elements, teaches that the polishing device is configured to flatten the first wafer before an exposure process to be conducted on the first wafer (see Shibue ¶[0097]: polishing head 1 is configured to flatten wafer W before the polished wafer W is subjected to the next exposure process; see also FIG. 4C and ¶[0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the polishing device of Kobata, as modified, to be configured to flatten the first wafer before an exposure process is conducted on the first wafer, as taught by Shibue. Shibue teaches that having a plurality of sensors and piezoelectric elements in the polishing table “reduce the variation in film thickness in the circumferential direction as compared with the initial film thickness distribution” (see FIG. 4C and ¶[0059]-[0061]). Shibue further teaches that such “variations in the film thickness distribution may cause the focus to be out of focus in the next exposure process, resulting in a decrease in the yield of semiconductor manufacturing,” so flattening the wafer before the wafer is subjected to a subsequent exposure process would maximize the product yield (¶[0060]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Poiesz (US 10310393 B2) teaches a substrate support incorporating piezoelectric elements.
Hariharan (US 20190240802 A1) teaches a method of polishing a substrate using piezoelectric sensors.
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/C.J./Examiner, Art Unit 3723
/DAVID S POSIGIAN/Supervisory Patent Examiner, Art Unit 3723
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