DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 14 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,469,181 hereinafter “181 Patent”. Although the claims at issue are not identical, they are not patentably distinct from each other because
Current Application
1. A semiconductor device, comprising: a substrate having an active region; a recess gate structure disposed in the substrate and intersecting the active region; a conductive pillar disposed over the substrate and electrically connected to the active region; a landing pad disposed on the conductive pillar and electrically connected to the conductive pillar; and a stack of dielectric layers disposed over the substrate and laterally surrounding the conductive pillar and the landing pad.
181 Patent
1. A memory device, comprising: a substrate, having a first active region and a second active region; a word line, formed in the substrate and intersected with the first and second active regions; a first conductive pillar and a second conductive pillar, disposed over the substrate, and overlapped with and electrically connected to the first and second active regions, respectively, wherein the first and second conductive pillars are arranged along a direction substantially parallel to an extending direction of the word line; a first landing pad and a second landing pad, disposed on the first and second conductive pillars, and overlapped with and electrically connected to the first and second conductive pillars, respectively, wherein sidewalls of the first and second conductive pillars are recessed from sidewalls of the first and second landing pads, wherein the first and second landing pads and the first and second conductive pillars are respectively made of different conductive materials, and a resistivity of the first and second landing pads is lower than a resistivity of the first and second conductive pillars; and a dielectric layer, laterally surrounding the first and second conductive pillars as well as the first and second landing pads, and having an air gap between the first and second conductive pillars.
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Claim 14 of the current application is anticipated by claim 1 of the 181 Patent.
Claim 15 of the current application is anticipated by claim 1 of the 181 Patent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 14 and 15 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Huang (US 2021/0407908) hereinafter “Huang”.
Regarding claim 1, Fig. 1B of Huang teaches a semiconductor device, comprising: a substrate (Item 100) having an active region (Item AA); a recess gate structure (Item 104) disposed in the substrate (Item 100) and intersecting the active region (Item AA); a conductive pillar (Item 116) disposed over the substrate (Item 100) and electrically connected to the active region (Item AA); a landing pad (Item CP) disposed on the conductive pillar (Item 116) and electrically connected to the conductive pillar (Item 116); and a stack of dielectric layers (Items 110) disposed over the substrate (Item 100) and laterally surrounding the conductive pillar (Item 116) and the landing pad (Item CP).
Regarding claim 14, Huang further teaches where the conductive pillar (Item 116) and the landing pad (Item CP) are made of different conductive materials (Paragraph 0029).
Regarding claim 15, Huang further teaches where a resistivity of the landing pad (Item CP) is less than (Paragraph 0006) a resistivity of the conductive pillar (Item 116).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2021/0407908) hereinafter “Huang” in view of Xie et al. (US 2014/0353734) hereinafter “Xie”.
Regarding claim 2, Huang teaches all of the elements of the claimed invention as stated above..
Fig. 1B of Huang further teaches where the recess gate structure (Item 104) comprises a first insulating layer (Item 106) concavely disposed in the substrate (Item 100) and comprising a U-shaped cross-sectional profile; a first filler layer (Item WL) disposed on the insulating layer (Item 104); and a capping dielectric layer (Item 108) disposed on the substrate (Item 100) and covering the first filler layer (Item WL).
Huang does not teach a first assisting layer conformally disposed on the first insulating layer and the substrate.
Fig. 1S of Xie teaches where a work function layer (Item 114; equivalent to a first assisting layer) is conformally disposed on a first insulating layer (Item 112) and a substrate (Item 102).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a first assisting layer conformally disposed on the first insulating layer and the substrate because the first assisting layer may act as a work functional material layer to tune the gate electrode structure (Xie Paragraph 0041).
Under an alternate interpretation of Xie, Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2021/0407908) hereinafter “Huang” in view of Xie et al. (US 2014/0353734) hereinafter “Xie”.
Regarding claim 2, Huang teaches all of the elements of the claimed invention as stated above..
Fig. 1B of Huang further teaches where the recess gate structure (Item 104) comprises a first insulating layer (Item 106) concavely disposed in the substrate (Item 100) and comprising a U-shaped cross-sectional profile; a first filler layer (Item WL) disposed on the insulating layer (Item 104); and a capping dielectric layer (Item 108) disposed on the substrate (Item 100) and covering the first filler layer (Item WL).
Huang does not teach a first assisting layer conformally disposed on the first insulating layer and the substrate.
Fig. 1S of Xie teaches where a barrier/adhesive layer (Item 154; equivalent to a first assisting layer) is conformally disposed on a first insulating layer (Item 112) and a substrate (Item 102).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a first assisting layer conformally disposed on the first insulating layer and the substrate because the first assisting layer may act as a barrier/adhesive material layer for the gate electrode structure (Xie Paragraph 0059).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2021/0407908) hereinafter “Huang” in view of Xie et al. (US 2014/0353734) hereinafter “Xie” and in further view of Cho et al. (US 2021/0057417) hereinafter “Cho”.
Regarding claim 3, the combination of Huang and Xie teaches all of the elements of the claimed invention as stated above except where a top surface of the first insulating layer is at a vertical level lower than a top surface of the substrate.
Fig. 2C of Cho teaches where a top surface of a first insulating layer (Item GI) is at a vertical level lower than a top surface of a substrate (Combination of Items 110, SD1 and ST).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a top surface of the first insulating layer be at a vertical level lower than a top surface of the substrate because it allows a cap layer to have a top surface coplanar with that of an active pattern (Cho Paragraph 0064).
Allowable Subject Matter
Claims 4-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, the prior art of record does not teach, suggest or motivate one having ordinary skill in the art to have the first assisting layer comprises a first step portion and a second step portion, wherein the first step portion of the first assisting layer is positioned adjacent to the top surface of the first insulating layer, and the second step portion of the first assisting layer is positioned adjacent to the top surface of the substrate along with the limitations of claims 1-3, from which claim 4 depends.
Claims 5-13 are also indicated as containing allowable subject matter as they depend from and include all of the elements of claim 4.
Citation of Pertinent Prior Art
Fig. 7 of Chiu et al. (US 2023/0422491) teaches where a work function layer (Item 64; 1st assisting layer) has a first step and second step and is adjacent to a first insulating layer (Item 62). However, Chiu does not teach where the second step is adjacent to a first insulating layer and a top surface of the substrate.
Fig. 30 of Chen et al. (US 11, 437, 484) teaches where assisting layers have multiple steps. However, Chen does not teach where a second step of a first assisting layer is adjacent to a first insulating layer and a top surface of a substrate.
Fig. 1F of Patil et al. (US 10,056,303) teaches a recessed gate where a work function layer (Item 113; 1st assisting layer) has a first step and is adjacent to a first insulating layer (Item 109). However, Patil does not teach a second step nor where the second step is adjacent to a first insulating layer and a top surface of the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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