DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 and 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention
Claim 1 recites “the pixel transistor” (line 11). There is insufficient antecedent basis for this limitation in the claim because it is unclear whether “the pixel transistor” in line 11 relates back to “pixel transistors” recited in line 6 or to set forth an additional pixel transistor.
Claim 16 recites “the pixel transistor” (line 12). There is insufficient antecedent basis for this limitation in the claim because it is unclear whether “the pixel transistor” in line 12 relates back to “pixel transistors” recited in lines 9-10 or to set forth an additional pixel transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 12-14, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0355859 to Yang et al. (hereinafter Yang) in view of Nakazawa et al. (US 2023/0411429, hereinafter Nakazawa).
With respect to claim 1, Yang discloses an image sensor (Yang, Figs. 1A, 6A, ¶0017- ¶0034, ¶0053- ¶0069) comprising:
a first layer (102) (Yang, Fig. 6A, ¶0054-¶0056) including a first substrate (101) having a first front surface (101f) and a first back surface (101b) opposite the first front surface (101f), a floating diffusion region (FD 612) in the first substrate (101), a first pad (112) (Yang, Fig. 6A, ¶0060), and a first conductive line (122/608, of the first interconnect 604) (Yang, Fig. 6A, ¶0059) connecting the floating diffusion region (FD 612) and the first pad (112); and
a second layer (104) (Yang, Fig. 6A, ¶0054, ¶0058, ¶0060, ¶0064) including a second substrate (103) having a second front surface (103f) and a second back surface (103b) opposite the second front surface (103f), pixel transistors (611) (Yang, Fig. 6A, ¶0058) on the second substrate (103), a second pad (120), and a second conductive line (122/608, of the second interconnect 630) (Yang, Fig. 6A, ¶0059) connecting one (611b) of the pixel transistors (611) and the second pad (120),
wherein the second layer (104) (Yang, Fig. 6A, ¶0054, ¶0060-¶0061) is bonded to the first layer (102), and
wherein the second conductive line (122/608, of the second interconnect 630) (Yang, Fig. 6A, ¶0059) is electrically connected to a lower portion of the pixel transistor (611).
Further, Yang does not specifically disclose that the second conductive line passes through the second substrates and is electrically connected to a lower portion of the pixel transistor.
However, Nakazawa teaches forming an imaging device (Nakazawa, Figs. 6, 13, 80, ¶0004-¶0006, ¶0231-¶0236, ¶0247-¶0334) of a three-dimensional structure comprising a first substrate (100) and a second substrate (200) that are stacked on each other to have improved area efficiency, wherein the first substrate (100) includes a first semiconductor layer (100S) and a first wiring layer (100T) and the second substrate (200) includes a second semiconductor layer (200S) and a second wiring layer (200T). The first substrate (100) and the second substrate (200) are electrically coupled to each other by through-electrode (120E) (Nakazawa, Figs. 6, 13, 80, ¶0233, ¶0308-¶0310, ¶0444) that passes through the second substrates (200S) and is electrically connected to a lower portion of the pixel transistor (e.g., amplification AMP transistor in Fig. 13 or reset transistor RST and AMP transistor in Fig. 80), and further the through-electrode (120E) electrically connects the pixel transistor (AMP in Fig. 13 or AMP and RST in Fig. 80) to the floating diffusion (FD), to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang by forming the first substrate and the second substrate stacked on each other and electrically coupled to each other by through-electrode as taught by Nakazawa to have the image sensor, wherein the second conductive line passes through the second substrates and is electrically connected to a lower portion of the pixel transistor, in order to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
Regarding claim 2, Yang in view of Nakazawa discloses the image sensor of claim 1. Further, Yang discloses the image sensor, wherein the second conductive line (122/608, of the second interconnect 630) (Yang, Fig. 6A, ¶0059) comprises a vertical conductive line (608) extending along a direction parallel to a stacking direction of the first layer (102) and the second layer (104), and a horizontal conductive line (122) extending along a direction perpendicular to the vertical conductive line, and wherein the vertical conductive line (608) is directly adjacent to the one (611b) of the pixel transistors (611), but does not specifically disclose that the vertical conductive line passes through the second substrate.
However, Nakazawa teaches forming the through-electrode (120E) (Nakazawa, Figs. 6, 13, 80, ¶0233, ¶0308-¶0310, ¶0444) that passes through the second substrates (200S) and is electrically connected to the pixel transistor (e.g., amplification AMP transistor in Fig. 13 or reset transistor RST and AMP transistor in Fig. 80), to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang/Nakazawa by arranging the pixel transistors on the second substrate as taught by Nakazawa, and forming the second conductive line including the through-electrode of Nakazawa to have the image sensor, wherein the vertical conductive line passes through the second substrate, in order to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
Regarding claim 3, Yang in view of Nakazawa discloses the image sensor of claim 1. Further, Yang discloses the image sensor, wherein the second conductive line (122/608, of the second interconnect 630) (Yang, Fig. 6A, ¶0058-¶0059) is electrically connected to a gate electrode of the one (611b) of the pixel transistors (611).
Regarding claim 4, Yang in view of Nakazawa discloses the image sensor of claim 3. Further, Yang discloses the image sensor, wherein the one (611b) (Yang, Fig. 6A, ¶0058) of the pixel transistors (611) is a source follower transistor.
Regarding claims 5-6, Yang in view of Nakazawa discloses the image sensor of claim 1. Further, Yang does not specifically disclose the image sensor, wherein the second conductive line is electrically connected to a drain region of the one of the pixel transistors (as claimed in claim 5); wherein one of the pixel transistors is a double conversion gain transistor (as claimed in claim 6).
However, Nakazawa teaches forming the through-electrode (120E) (Nakazawa, Figs. 80, 93-94, ¶0444, ¶0466) electrically connected to a source/drain region (RS) of the one of the pixel transistors including reset transistor (RST) (Nakazawa, Fig. 80), or FD conversion gain switching transistor (FDG) (Nakazawa, Figs. 93-94), to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444, ¶0466).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang/Nakazawa by arranging the pixel transistors on the second substrate as taught by Nakazawa, and forming the second conductive line including the through-electrode of Nakazawa to have the image sensor, wherein the second conductive line is electrically connected to a drain region of the one of the pixel transistors (as claimed in claim 5); wherein one of the pixel transistors is a double conversion gain transistor (as claimed in claim 6), in order to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
Regarding claim 7, Yang in view of Nakazawa discloses the image sensor of claim 5. Further, Yang does not specifically disclose the image sensor, wherein the second layer further includes a third conductive line electrically connected to the drain region of the one of the pixel transistors on the second front surface of the second layer, and wherein the third conductive line is electrically connected to a gate electrode of another one of the pixel transistors.
However, Nakazawa teaches forming the through-electrode (120E) (Nakazawa, Fig. 80, ¶0444) electrically connected to a source/drain region (RS) of the one of the pixel transistors including reset transistor (RST) (Nakazawa, Fig. 80) on the second front surface (e.g., 200S1) of the second layer (200S), and is electrically connected to a gate electrode (AG) of another one (amplification AMP) of the pixel transistors, to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang/Nakazawa by arranging the pixel transistors on the second substrate as taught by Nakazawa, and forming the second conductive line including the through-electrode of Nakazawa to have the image sensor, wherein the second layer further includes a third conductive line electrically connected to the drain region of the one of the pixel transistors on the second front surface of the second layer, and wherein the third conductive line is electrically connected to a gate electrode of another one of the pixel transistors, in order to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
With respect to claim 12, Yang discloses an image sensor (Yang, Figs. 1A-1B, 6A, ¶0017- ¶0034, ¶0053- ¶0069) comprising:
a pixel array including a plurality of pixels (126) (Yang, Figs. 1A-1B, 6A, ¶0024- ¶0025, ¶0054), wherein the plurality of pixels (126) include a first pixel and a second pixel adjacent to each other,
wherein each of the first pixel and the second pixel includes a first layer (102) (Yang, Fig. 6A, ¶0054-¶0056) and a second layer (104) (Yang, Fig. 6A, ¶0054, ¶0058, ¶0060, ¶0064) bonded to the first layer,
wherein the first layer (102) (Yang, Fig. 6A, ¶0054-¶0056) includes a first substrate (101) having a first front surface (101f) and a first back surface (101b) opposite the first front surface (101f), a floating diffusion region (FD 612) in the first substrate (101), at least one first pad (112) (Yang, Fig. 6A, ¶0060), and a first conductive line (122/608, of the first interconnect 604) (Yang, Fig. 6A, ¶0059) connecting the floating diffusion region (FD 612) and the at least one first pad (112),
wherein the second layer (104) (Yang, Fig. 6A, ¶0054, ¶0058, ¶0060, ¶0064) includes a second substrate (103) having a second front surface (103f) and a second back surface (103b) opposite the second front surface (103f), pixel transistors (611) (Yang, Fig. 6A, ¶0058) on the second substrate (103), a second pad (120), and a second conductive line (122/608, of the second interconnect 630) (Yang, Fig. 6A, ¶0059) connecting one (611b) of the pixel transistors (611) and the second pad (120), and
wherein the second conductive line (122/608, of the second interconnect 630) (Yang, Fig. 6A, ¶0059) is electrically connected to a lower portion of the one of the pixel transistors (611).
Further, Yang does not specifically disclose that the second conductive line passes through the second substrates and is electrically connected to a lower portion of the one of the pixel transistors.
However, Nakazawa teaches forming an imaging device (Nakazawa, Figs. 6, 13, 80, ¶0004-¶0006, ¶0231-¶0236, ¶0247-¶0334) of a three-dimensional structure comprising a first substrate (100) and a second substrate (200) that are stacked on each other to have improved area efficiency, wherein the first substrate (100) includes a first semiconductor layer (100S) and a first wiring layer (100T) and the second substrate (200) includes a second semiconductor layer (200S) and a second wiring layer (200T). The first substrate (100) and the second substrate (200) are electrically coupled to each other by through-electrode (120E) (Nakazawa, Figs. 6, 13, 80, ¶0233, ¶0308-¶0310, ¶0444) that passes through the second substrates (200S) and is electrically connected to a lower portion of the pixel transistor (e.g., amplification AMP transistor in Fig. 13 or reset transistor RST and AMP transistor in Fig. 80), and further the through-electrode (120E) electrically connects the pixel transistor (AMP in Fig. 13 or AMP and RST in Fig. 80) to the floating diffusion (FD), to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang by forming the first substrate and the second substrate stacked on each other and electrically coupled to each other by through-electrode as taught by Nakazawa to have the image sensor, wherein the second conductive line passes through the second substrates and is electrically connected to a lower portion of the one of the pixel transistors, in order to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
Regarding claim 13, Yang in view of Nakazawa discloses the image sensor of claim 12.
Further, Yang does not specifically disclose that the floating diffusion region of the first pixel and the floating diffusion region of the second pixel are electrically connected to a same first pad from among the at least one first pad.
However, Nakazawa teaches forming an imaging device (Nakazawa, Figs. 6, 13, 80, ¶0004-¶0006, ¶0231-¶0236, ¶0247-¶0334), wherein the floating diffusion region (FD) of the first pixel (e.g., 541 of the pixel sharing unit 539) and the floating diffusion region (FD) of the second pixel (e.g., another pixel 541 of the pixel sharing unit 539) are electrically connected to a same first pad (120) (Nakazawa, Fig. 6, ¶0250) from among the at least one first pad.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang/Nakazawa by forming the first substrate and the second substrate stacked on each other and electrically coupled to each other by through-electrode as taught by Nakazawa to have the image sensor, wherein the floating diffusion region of the first pixel and the floating diffusion region of the second pixel are electrically connected to a same first pad from among the at least one first pad, in order to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
Regarding claim 14, Yang in view of Nakazawa discloses the image sensor of claim 12.
Further, Yang discloses the image sensor, wherein the floating diffusion region (612) (Yang, Fig. 6A, ¶0055-¶0057) of the first pixel (126) and the floating diffusion region (612) of the second pixel (126) are electrically connected to different first pads (112) from among the at least one first pad.
With respect to claim 16, Yang discloses an image sensor (Yang, Figs. 1A-1B, 6A, ¶0017- ¶0034, ¶0053- ¶0069) comprising a pixel array region (Yang, Figs. 1A-1B, 6A, ¶0024- ¶0025, ¶0054), wherein the pixel array region includes a first layer (102) (Yang, Fig. 6A, ¶0054-¶0056) and a second layer (104) (Yang, Fig. 6A, ¶0054, ¶0058, ¶0060, ¶0064) bonded to the first layer,
wherein in the pixel array region the first layer (102) (Yang, Fig. 6A, ¶0054-¶0056) includes a first substrate (101) having a first front surface (101f) and a first back surface (101b) opposite the first front surface (101f), a floating diffusion region (FD 612) in the first substrate (101), a first pad (112) (Yang, Fig. 6A, ¶0060), and a first conductive line (122/608, of the first interconnect 604) (Yang, Fig. 6A, ¶0059) connecting the floating diffusion region (FD 612) and the first pad (112),
wherein in the pixel array region the second layer (104) (Yang, Fig. 6A, ¶0054, ¶0058, ¶0060, ¶0064) includes a second substrate (103) having a second front surface (103f) and a second back surface (103b) opposite the second front surface (103f), pixel transistors (611) (Yang, Fig. 6A, ¶0058) on the second substrate (103), a second pad (120), and a second conductive line (122/608, of the second interconnect 630) (Yang, Fig. 6A, ¶0059) connecting one (611b) of the pixel transistors (611) and the second pad (120), and the second conductive line (122/608, of the second interconnect 630) (Yang, Fig. 6A, ¶0059) being electrically connected to a lower portion of the pixel transistor (611).
Further, Yang does not specifically disclose a pad region, wherein the pad region includes a first layer and a second layer bonded to the first layer, the second conductive line passes through the second substrates and being electrically connected to a lower portion of the pixel transistor, and wherein in the pad region the first layer includes a main via penetrating the first substrate, and a signal pad on the main via.
However, Nakazawa teaches forming an imaging device (Nakazawa, Figs. 6, 13, 80, ¶0004-¶0006, ¶0231-¶0236, ¶0247-¶0334) of a three-dimensional structure comprising a pixel array region (540) and a pad region (540B), wherein each of the pixel array region (540) (Nakazawa, Fig. 6, ¶0232-¶0236, ¶0247, ¶0305) and the pad region (540B) includes a first layer (100) and a second layer (200) bonded to the first layer to have improved area efficiency, wherein the first layer (100) includes a first semiconductor layer (100S) and a first wiring layer (100T) and the second layer (200) includes a second semiconductor layer (200S) and a second wiring layer (200T), and wherein in the pad region (540B), the first layer (100) includes a main via (e.g., coupling hole H1/H2 filled with a conductive material) (Nakazawa, Fig. 6, ¶0236) penetrating the first substrate (100S), and a signal pad (e.g., contact pads 201/301 and 202/302 to couple the input/output section 510A/510B to the main via in the coupling hole H1/H2) (Nakazawa, Fig. 6, ¶0233) on the main via. The first layer (100) and the second layer (200) are electrically coupled to each other by through-electrode (120E) (Nakazawa, Figs. 6, 13, 80, ¶0233, ¶0308-¶0310, ¶0444) that passes through the second substrates (200S) and is electrically connected to a lower portion of the pixel transistor (e.g., amplification AMP transistor in Fig. 13 or reset transistor RST and AMP transistor in Fig. 80), and further the through-electrode (120E) electrically connects the pixel transistor (AMP in Fig. 13 or AMP and RST in Fig. 80) to the floating diffusion (FD), to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang by forming the first substrate and the second substrate stacked on each other and electrically coupled to each other by through-electrode, and the peripheral regions including through holes filled with a conductive material as taught by Nakazawa to have the image sensor comprising: a pad region, wherein the pad region includes a first layer and a second layer bonded to the first layer, the second conductive line passes through the second substrates and being electrically connected to a lower portion of the pixel transistor, and wherein in the pad region the first layer includes a main via penetrating the first substrate, and a signal pad on the main via, in order to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
Regarding claims 17 and 18, Yang in view of Nakazawa discloses the image sensor of claim 16. Further, Yang discloses the image sensor, wherein the pixel array region further includes a third layer (602) (Yang, Fig. 6A, ¶0054, ¶0065) bonded to the second layer (104), wherein the third layer (602) includes a third substrate (641) having a third front surface (641f), a third back surface opposite the third front surface, and logic transistors (652), but does not specifically disclose that each of the pixel array region and the pad region further includes a third layer bonded to the second layer (as claimed in claim 17); wherein the logic transistors and the signal pad are electrically connected to each other (as claimed in claim 18).
However, Nakazawa teaches forming an imaging device (Nakazawa, Fig. 6, ¶0247, ¶0314), wherein each of the pixel array region (540) and the pad region (540B) further includes a third layer (300) bonded to the second layer (200), wherein the third layer (300) includes a third substrate (300S) having a third front surface, a third back surface opposite the third front surface, and logic transistors (e.g., 510, 520, 550, and 560 circuits including transistors for processing, timing control, and input/output), wherein the logic transistors (e.g., input/output circuits 510/520 including transistors) and the signal pad (201/301 and 202/302) are electrically connected to each other.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang/Nakazawa by forming the third substrate coupled to the second substrate as taught by Nakazawa to have the image sensor, wherein each of the pixel array region and the pad region further includes a third layer bonded to the second layer (as claimed in claim 17); wherein the logic transistors and the signal pad are electrically connected to each other (as claimed in claim 18), in order to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0355859 to Yang in view of Nakazawa (US 2023/0411429) as applied to claim 1, and further in view of Oh (US 2018/0213173).
Regarding claim 6, Yang in view of Nakazawa discloses the image sensor of claim 5. Further, Yang does not specifically disclose the image sensor, wherein one of the pixel transistors is a double conversion gain transistor.
However, Oh teaches forming an image sensor comprising a dual conversion gain transistor (54) (Oh, Figs. 5, 8, 10, ¶0001, ¶0019-¶0023, ¶0041-¶0045) having a gate terminal that is controlled using dual conversion gain signal to operate in a high conversion gain mode for a high resolution mode and a low conversion gain mode for a low resolution mode (Oh, Figs. 5, 8, 10, ¶0044, ¶0045), to provide an image sensor with phase detection capabilities.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang/Nakazawa by forming pixel transistors including a dual conversion gain transistor as taught by Oh to have the image sensor, wherein one of the pixel transistors is a double conversion gain transistor, in order to provide an image sensor with phase detection capabilities (Oh, ¶0001, ¶0019, ¶0044, ¶0045).
Claims 8-11 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0355859 to Yang in view of Nakazawa (US 2023/0411429) as applied to claim 1 (claim 12), and further in view of Horikoshi (US 2022/0077215).
Regarding claim 8, Yang in view of Nakazawa discloses the image sensor of claim 1.
Further, Yang discloses the image sensor, wherein the second conductive line (122/608, of the second interconnect 630) (Yang, Fig. 6A, ¶0059) includes a vertical conductive line (608) extending along a direction parallel to a stacking direction of the first layer (102) and the second layer (104), and a horizontal conductive line (122) extending along a direction perpendicular to the vertical conductive line, but does not specifically disclose the image sensor, wherein the vertical conductive line includes a first vertical conductive line passing through the second substrate and electrically connected to a gate electrode of the one of the pixel transistors, and a second vertical conductive line passing through the second substrate and electrically connected to a drain region of another one of the pixel transistors, and wherein the first vertical conductive line and the second vertical conductive line are electrically connected to each other by the horizontal conductive line.
However, Horikoshi teaches forming an image sensor (Horikoshi, Figs. 10A, 15, ¶0051-¶0106) comprising a first substrate (1) (Horikoshi, Figs. 10A, 15, ¶0065) and a second substrate (3) including a semiconductor layer (31) (Horikoshi, Figs. 10A, 15, ¶0073-¶0077) and having pixel transistors (e.g., amplifying transistor 32aa/32ab, selective transistor 32b, and reset transistor 32c), and a vertical conductive line (21) (Horikoshi, Figs. 10A, 15, ¶0063, ¶0075, ¶0104-¶0106) that includes a first vertical conductive line (21a) passing through the second substrate (31) and electrically connected to a gate electrode (34a) of the one (32aa) of the pixel transistors, and a second vertical conductive line (21b) passing through the second substrate (31) and electrically connected to a gate region (34b) of another one (32ab) of the pixel transistors, and wherein the first vertical conductive line (21a) and the second vertical conductive line (21b) are electrically connected to each other by the horizontal conductive line (38a), and further the amplifying transistor (32aa/32ab) is connected to the source/drain region of the reset transistor (32c) (Horikoshi, Figs. 10A, 15, ¶0075, ¶0077), to provide high-resolution solid-sate imaging device which effectively utilizes the area resources of the semiconductor substrates (Horikoshi, ¶0006, ¶0065, ¶0073-¶0075).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang/Nakazawa by arranging the pixel transistors on the second substrate as taught by Horikoshi to have the image sensor, wherein the vertical conductive line includes a first vertical conductive line passing through the second substrate and electrically connected to a gate electrode of the one of the pixel transistors, and a second vertical conductive line passing through the second substrate and electrically connected to a drain region of another one of the pixel transistors, and wherein the first vertical conductive line and the second vertical conductive line are electrically connected to each other by the horizontal conductive line, in order to provide high-resolution solid-sate imaging device which effectively utilizes the area resources of the semiconductor substrates (Horikoshi, ¶0006, ¶0065, ¶0073-¶0075).
Regarding claim 9, Yang in view of Nakazawa and Horikoshi discloses the image sensor of claim 8. Further, Yang discloses the image sensor, wherein the second layer (104) further includes a first insulating layer (e.g., dielectric layer 636 of the wiring layer 634 disposed on a back side 103b of the second substrate 103 and under the substrate 103) (Yang, Fig. 6A, ¶0064) on the second back surface (103b) of the second substrate (103), but does not specifically disclose that the horizontal conductive line is in the first insulating layer on the second back surface.
However, Horikoshi teaches forming the horizontal conductive line (38a) (Horikoshi, Figs. 10A, 15, ¶0077) in the first insulating layer (37) under the second substrate (31).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang/Nakazawa/Horikoshi by arranging the pixel transistors on the second substrate as taught by Horikoshi to have the image sensor, wherein the horizontal conductive line is in the first insulating layer on the second back surface, in order to provide high-resolution solid-sate imaging device which effectively utilizes the area resources of the semiconductor substrates (Horikoshi, ¶0006, ¶0065, ¶0073-¶0075).
Regarding claim 10, Yang in view of Nakazawa and Horikoshi discloses the image sensor of claim 8. Further, Yang discloses the image sensor, wherein the second layer (104) further includes a first insulating layer (e.g., dielectric layer 606) (Yang, Fig. 6A, ¶0059) on the second front surface (103f) of the second substrate (103), but does not specifically disclose that the first vertical conductive line and the second vertical conductive line are spaced apart from the first insulating layer.
However, Nakazawa teaches forming a first insulating layer (e.g., an insulating layer of the wiring layer 400T) (Nakazawa, Figs. 6, 13, 88, ¶0456-¶0458) on the second front surface (200S1) of the second substrate (200S), wherein the first vertical conductive line (120E) and the second vertical conductive line (120E) are spaced apart from the first insulating layer (400T) by a substrate layer (400S), to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang/Nakazawa/Horikoshi by arranging the pixel transistors on the second substrate as taught by Nakazawa, and forming the second conductive line including the first and second through-electrodes of Nakazawa to have the image sensor, wherein the first vertical conductive line and the second vertical conductive line are spaced apart from the first insulating layer, in order to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
Regarding claim 11, Yang in view of Nakazawa and Horikoshi discloses the image sensor of claim 8. Further, Yang discloses the image sensor, wherein the first vertical conductive line (e.g., 608, of the first interconnect 604) (Yang, Fig. 6A, ¶0059) overlaps the gate electrode of the one (611b) of the pixel transistors (611) along the direction parallel to the stacking direction of the first layer (102) and the second layer (104), but does not specifically disclose that the second vertical conductive line overlaps the drain region of the another one of the pixel transistors along the direction parallel to the stacking direction of the first layer and the second layer.
However, Nakazawa teaches forming the second vertical conductive line (120E) (Nakazawa, Figs. 6, 13, 88, ¶0456-¶0458) that overlaps the source/drain region of the another one (e.g. FDG pixel transistor) of the pixel transistors along the direction parallel to the stacking direction of the first layer (100) and the second layer (200/400).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang/Nakazawa/Horikoshi by arranging the pixel transistors on the second substrate as taught by Nakazawa, and forming the second conductive line including the first and second through-electrodes of Nakazawa to have the image sensor, wherein the second vertical conductive line overlaps the drain region of the another one of the pixel transistors along the direction parallel to the stacking direction of the first layer and the second layer, in order to shorten wiring line length between the floating diffusion and pixel transistor, to reduce a wiring capacity, and thus to improve conversion efficiency, to reduce noise, and to improve area efficiency (Nakazawa, ¶0004-¶0006, ¶0310, ¶0444).
Regarding claim 15, Yang in view of Nakazawa discloses the image sensor of claim 12.
Further, Yang discloses the image sensor, wherein the first conductive line (122/608, of the first interconnect 604) (Yang, Fig. 6A, ¶0059) includes a vertical conductive line (608) extending along a direction parallel to a stacking direction of the first layer (102) and the second layer (104), and at least one horizontal conductive line (122) extending along a direction perpendicular to the vertical conductive line, wherein the vertical conductive line (608) includes a first vertical conductive line electrically connected to the floating diffusion region (612) of the first pixel, and a second vertical conductive line (608) electrically connected to the floating diffusion region (612) of the second pixel, but does not specifically disclose the image sensor, wherein the first vertical conductive line and the second vertical conductive line are electrically connected to a same horizontal conductive line from among the at least one horizontal conductive line.
However, Horikoshi teaches forming an image sensor (Horikoshi, Figs. 10A, 15, ¶0051-¶0106) comprising a first substrate (1) (Horikoshi, Figs. 10A, 15, ¶0065) and a second substrate (3) including a semiconductor layer (31) (Horikoshi, Figs. 10A, 15, ¶0073-¶0077) and having pixel transistors (e.g., amplifying transistor 32aa/32ab, selective transistor 32b, and reset transistor 32c), and a vertical conductive line (21) (Horikoshi, Figs. 10A, 15, ¶0063, ¶0075, ¶0104-¶0106) that includes a first vertical conductive line (21a) passing through the second substrate (31) and electrically connected to a gate electrode (34a) of the one (32aa) of the pixel transistors, and a second vertical conductive line (21b) passing through the second substrate (31) and electrically connected to a gate region (34b) of another one (32ab) of the pixel transistors, and wherein the first vertical conductive line (21a) and the second vertical conductive line (21b) are electrically connected to each other by the horizontal conductive line (38a), and further the amplifying transistor (32aa/32ab) is connected to the source/drain region of the reset transistor (32c) (Horikoshi, Figs. 10A, 15, ¶0075, ¶0077), to provide high-resolution solid-sate imaging device which effectively utilizes the area resources of the semiconductor substrates (Horikoshi, ¶0006, ¶0065, ¶0073-¶0075).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang/Nakazawa by arranging the pixel transistors on the second substrate as taught by Horikoshi to have the image sensor, wherein the first vertical conductive line and the second vertical conductive line are electrically connected to a same horizontal conductive line from among the at least one horizontal conductive line, in order to provide high-resolution solid-sate imaging device which effectively utilizes the area resources of the semiconductor substrates (Horikoshi, ¶0006, ¶0065, ¶0073-¶0075).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0355859 to Yang in view of Nakazawa (US 2023/0411429) as applied to claim 18, and further in view of Kobayashi (US Patent No. 10,804,310).
Regarding claim 19, Yang in view of Nakazawa discloses the image sensor of claim 18.
Further, Yang does not specifically disclose the image sensor, wherein in the pad region the second layer further includes a third conductive line on the second front surface of the second substrate, a middle via between the third conductive line and the second conductive line, and a third pad connected to an opposite side of the middle via with respect to the third conductive line, and wherein the third layer further includes a fourth pad in contact with the third pad and a fourth conductive line connecting the fourth pad and the logic transistors.
However, Kobayashi teaches forming a photoelectric conversion device (Kobayashi, Fig. 21, Col. 1, lines 47-67; Col. 2, lines 1-11; Col. 21, lines 60-67; Col. 22, lines 1-36) comprising a pad region (402), wherein in the pad region (402), the second layer (201) further includes a third conductive line (e.g., wiring layer 207) on the second front surface (205) of the second substrate (204), a middle via (228b) between the third conductive line (e.g., wiring layer 207) and the second conductive line (e.g., wiring 220), and a third pad (227b) connected to an opposite side of the middle via (227b) with respect to the third conductive line, and wherein the third layer (301) further includes a fourth pad (323b) in contact with the third pad (227b) and a fourth conductive line (e.g., wiring layer 307) connecting the fourth pad (323b) and the transistors of the third layer (301), to provide photoelectric conversion device with improved characteristics and reliability (Kobayashi, Col. 1, lines 47-67; Col. 2, lines 1-11; Col. 21, lines 60-67; Col. 22, lines 1-36).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang/Nakazawa by arranging third chip on the second chip as taught by Kobayashi, wherein the third chip includes logic transistors to have the image sensor, wherein in the pad region the second layer further includes a third conductive line on the second front surface of the second substrate, a middle via between the third conductive line and the second conductive line, and a third pad connected to an opposite side of the middle via with respect to the third conductive line, and wherein the third layer further includes a fourth pad in contact with the third pad and a fourth conductive line connecting the fourth pad and the logic transistors, in order to provide photoelectric conversion device with improved characteristics and reliability (Kobayashi, Col. 1, lines 47-67; Col. 2, lines 1-11; Col. 21, lines 60-67; Col. 22, lines 1-36).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0355859 to Yang in view of Nakazawa (US 2023/0411429) and Kobayashi (US Patent No. 10,804,310) as applied to claim 19, and further in view of Lee et al. (US 2021/0057478, hereinafter Lee).
Regarding claim 20, Yang in view of Nakazawa discloses the image sensor of claim 19.
Further, Yang does not specifically disclose the image sensor, wherein in the pad region the first conductive line and the second conductive line are configured to have a grid shape.
However, Lee teaches forming an image sensor comprising a pad region (PR) (Lee, Fig. 3, ¶0005-¶0007, ¶0047-¶0106, ¶0117-¶0124) including the first conductive line (e.g., first wiring structure IS1, including a plurality of conductive layers 132 connected to each other with vias 134 to form a grid shape) and the second conductive line (e.g., the second wiring structure IS2, including a plurality of conductive layers connected to each other with vias to form a grid shape) configured to have a grid shape, wherein the first conductive layer (IS1) contacts through via (160), to reduce the electrical resistance between the through via (160) and the first conductive layer (IS1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the image sensor of Yang/Nakazawa/Kobayashi by forming the first and second conductive lines as first and second wiring structures of Lee including a plurality of conductive layers connected to each other as taught by Lee to have the image sensor, wherein in the pad region the first conductive line and the second conductive line are configured to have a grid shape, in order to reduce the electrical resistance between the through via and the first conductive layer, and thus to improve performance of the image sensor (Lee, ¶0005-¶0007, ¶0047, ¶0075, ¶0124).
Conclusion
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/NATALIA A GONDARENKO/ Primary Examiner, Art Unit 2891
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