DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 10-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suzuki et al. (US 2023/0170018 A1 hereinafter referred to as “Suzuki”).
With respect to claim 1, Suzuki discloses, in Figs.1-28, an information reading method of a self-selecting memory device (140), the self-selecting memory device (140) including a first electrode (141), a second electrode (142), and a memory layer (143) therebetween (see Par.[0043]-[0045] wherein the resistance change memory portion 140 has a structure in which the electrode 141, resistance change material layer 143, and electrode 142 are stacked in the Z-direction of FIG. 2), the memory layer (143) including a chalcogenide-based material, having Ovonic threshold switching characteristics, and configured to have a threshold voltage that changes to a set threshold voltage or a reset threshold voltage higher than the set threshold voltage according to polarity and intensity of a voltage applied to the memory layer (see Par.[0058] wherein it is possible to further set, in addition to the two states (low-resistance state, high-resistance state) set to the resistance change memory portion 140, two states to the selector portion 150; see Par.[0068]-[0072] wherein it is possible to set the four states to the memory cell 130 and store the four-value data in the memory cell 130 on the basis of the two states (low-resistance state, high-resistance state) of the resistance change memory portion 140 and two states (positive polarity state, negative polarity state) of the selector portion 150; by setting the two states (low-resistance state, high-resistance state) to the resistance change memory portion 140 and by setting the two states (positive polarity state, negative polarity state) to the selector portion 150, it is possible to set the four states to the memory cell 130 and store the four-value data in the memory cell 130; it is submitted that Ovonic threshold switching is a phenomenon in certain chalcogenide materials where the material abruptly transitions from a high-resistance state to a low-resistance state when a threshold voltage is exceeded, enabling controlled current flow in memory devices), the information reading method comprising: reading a data value stored in the memory layer by applying, to the memory layer as a read voltage, a voltage lower than the set threshold voltage (see Par.[0073]-[0079] wherein the distribution (a) of FIG. 14 relates to the cases where: the memory cell 130 has a second threshold voltage Vth2 of the positive polarity having an absolute value greater than the absolute value of the first threshold voltage Vth1 with respect to the read voltage of the positive polarity; the memory cell 130 has a second threshold voltage Vth2 of the positive polarity having an absolute value greater than the absolute value of the first threshold voltage Vth1 with respect to the read voltage of the positive polarity; the memory cell 130 has a third threshold voltage Vth3 of the positive polarity having an absolute value greater than the absolute value of the second threshold voltage Vth2 with respect to the read voltage of the positive polarity; the memory cell 130 has a fourth threshold voltage Vth4 of the positive polarity having an absolute value greater than the absolute value of the third threshold voltage Vth3 with respect to the read voltage of the positive polarity).
With respect to claim 2, Suzuki discloses, in Figs.1-28, the information reading method, wherein a level of the read voltage is about 40 % to about 90 % of a level of the set threshold voltage (see Fig.14 wherein, for example, level of VRD1/Vth2=2/3 or 66.66%; see Par.[0090] wherein it should be noted that although in the voltage applying operation shown in FIGS. 15 to 18, the absolute value of the voltage VSET of the positive polarity and absolute value of the voltage −VSET of the negative polarity are identical to each other, the absolute value of one of the above voltages may be within the range of 80% to 120% of the absolute value of the other of the voltages; likewise, although the absolute value of the voltage VRST of the positive polarity and absolute value of the voltage −VRST of the negative polarity are identical to each other, the absolute value of one of the above voltages may be within the range of 80% to 120% of the absolute value of the other of the voltages).
With respect to claim 3, Suzuki discloses, in Figs.1-28, the information reading method, wherein the level of the read voltage is about 60 % to about 80 % of the level of the set threshold voltage (see Fig.14 wherein, for example, level of VRD1/Vth2=2/3 or 66.66%; see Par.[0090] wherein it should be noted that although in the voltage applying operation shown in FIGS. 15 to 18, the absolute value of the voltage VSET of the positive polarity and absolute value of the voltage −VSET of the negative polarity are identical to each other, the absolute value of one of the above voltages may be within the range of 80% to 120% of the absolute value of the other of the voltages; likewise, although the absolute value of the voltage VRST of the positive polarity and absolute value of the voltage −VRST of the negative polarity are identical to each other, the absolute value of one of the above voltages may be within the range of 80% to 120% of the absolute value of the other of the voltages).
With respect to claim 4, Suzuki discloses, in Figs.1-28, the information reading method, wherein the reading reads the data value stored in the memory layer by measuring a current flowing through the memory layer at the read voltage (see Par.[0096] wherein when the read voltage VRD1 is applied to the memory cell 130, if the memory cell 130 enters the on-state (if an on-current flows through the memory cell 130), the determining circuit 320 of FIG. 8 determines that the first data corresponding to the first memory state (low-resistance state/positive polarity state) is stored in the memory cell 130 (S12, S13); see Par.[0098] wherein When the read voltage VRD2 is applied to the memory cell 130, if the memory cell 130 enters the on-state (if an on-current flows through the memory cell 130), the determining circuit 320 of FIG. 8 determines that the second data corresponding to the second memory state (low-resistance state/negative polarity state) is stored in the memory cell 130 (S15, S16); see Par.[0101] wherein When the read voltage VRD3 is applied to the memory cell 130, if the memory cell 130 enters the on-state (if an on-current flows through the memory cell 130), the determining circuit 320 of FIG. 8 determines that the third data corresponding to the third memory state (high-resistance state/positive polarity state) is stored in the memory cell 130 (S19, S20)).
With respect to claim 5, Suzuki discloses, in Figs.1-28, the information reading method, wherein, when the current flowing through the memory layer is measured as a relatively high current value, the memory layer is read as set, and when the current flowing through the memory layer is measured as a relatively low current value, the memory layer is read as reset (see Par.[0081]-[0088] wherein FIG. 15 is a view showing a voltage applying operation at the time when the first memory state (low-resistance state/positive polarity state) is set to the memory cell 130; more specifically, FIG. 15 is a timing chart showing the voltage to be applied to the memory cell 130 and current flowing through the memory cell 130; FIG. 16 is a view showing a voltage applying operation at the time when the second memory state (low-resistance state/negative polarity state) is set to the memory cell 130. More specifically, FIG. 16 is a timing chart showing a voltage to be applied to the memory cell 130 and current flowing through the memory cell 130; FIG. 17 is a view showing a voltage applying operation at the time when the third memory state (high-resistance state/positive polarity state) is set to the memory cell 130. More specifically, FIG. 17 is a timing chart showing a voltage to be applied to the memory cell 130 and current flowing through the memory cell 130; FIG. 18 is a view showing a voltage applying operation at the time when the fourth memory state (high-resistance state/negative polarity state) is set to the memory cell 130. More specifically, FIG. 18 is a timing chart showing a voltage to be applied to the memory cell 130 and current flowing through the memory cell 130; see Par.[0115]-[0122] wherein First, as shown in FIG. 24 (a) the memory cell 130 enters the on-state (if an on-current flows through the memory cell 130), the determining circuit 320 of FIG. 8 determines that the first data corresponding to the first memory state (low-resistance state/positive polarity state) is stored in the memory cell 130 (S32, S33)).
With respect to claim 6, Suzuki discloses, in Figs.1-28, the information reading method, wherein the relatively high current value is 10 times or more the relatively low current value (see Par.[0111] wherein the threshold voltage distribution shown in FIG. 14 and threshold voltage distribution shown in FIG. 22, it is possible to reduce the number of times (e.g.; 10 times) the rewrite is carried out; it is possible to determine the four states (four-value data) of the memory cell 130 and make the number of times (e.g.; 10 times) of the rewrite once).
With respect to claim 7, Suzuki discloses, in Figs.1-28, the information reading method, wherein a polarity of the read voltage is positive (+) (see Par.[0095]-[0098] wherein FIG. 21 is a timing chart showing a voltage applying operation at the time when a rewrite is carried out; the read voltage VRD1 having the positive polarity in (+); see Par.[0102]-[01111] wherein after applying the read voltage VRD3 of the positive polarity to the memory cell 130 as shown in FIG. 21 (b), a rewrite voltage of the positive polarity is applied to the memory cell 130; see Par.[0115]-[0119] wherein as shown in FIG. 24 (a) after applying the read voltage VRD3 of the positive polarity to the memory cell 130 as shown in FIG. 21 (b), a rewrite voltage of the positive polarity is applied to the memory cell 130).
With respect to claim 8, Suzuki discloses, in Figs.1-28, the information reading method, wherein the memory layer includes a chalcogen element including at least one of Se, Te, or S, and at least one of Ge, As, or Sb (see Par.[0045] wherein the resistance change material layer 143 of the resistance change memory portion 140 contains therein antimony (Sb) and tellurium (Te). The resistance change material layer 143 is formed of, for example, GeSbTe containing therein germanium (Ge), antimony (Sb), and tellurium (Te)).
With respect to claim 10, Suzuki discloses, in Figs.1-28, an information reading method of a self-selecting memory device, the self-selecting memory device (140) including a first electrode (141), a second electrode (142), and a memory layer (143) therebetween (see Par.[0043]-[0045] wherein the resistance change memory portion 140 has a structure in which the electrode 141, resistance change material layer 143, and electrode 142 are stacked in the Z-direction of FIG. 2), the memory layer including a chalcogenide-based material, having Ovonic threshold switching characteristics, and configured to have a threshold voltage that changes to a set threshold voltage or a reset threshold voltage higher than the set threshold voltage according to polarity and intensity of a voltage applied to the memory layer (see Par.[0058] wherein it is possible to further set, in addition to the two states (low-resistance state, high-resistance state) set to the resistance change memory portion 140, two states to the selector portion 150; see Par.[0068]-[0072] wherein it is possible to set the four states to the memory cell 130 and store the four-value data in the memory cell 130 on the basis of the two states (low-resistance state, high-resistance state) of the resistance change memory portion 140 and two states (positive polarity state, negative polarity state) of the selector portion 150; by setting the two states (low-resistance state, high-resistance state) to the resistance change memory portion 140 and by setting the two states (positive polarity state, negative polarity state) to the selector portion 150, it is possible to set the four states to the memory cell 130 and store the four-value data in the memory cell 130; it is submitted that Ovonic threshold switching is a phenomenon in certain chalcogenide materials where the material abruptly transitions from a high-resistance state to a low-resistance state when a threshold voltage is exceeded, enabling controlled current flow in memory devices), the information reading method comprising: reading a data value stored in the memory layer by applying, to the memory layer as a read voltage, a voltage at a critical point (ton) immediately before a slope of a set curve changes rapidly, the voltage at the critical point being lower than the set threshold voltage in a current-voltage characteristic curve for the memory layer (see Par.[0073]-[0079] wherein the distribution (a) of FIG. 14 relates to the cases where: the memory cell 130 has a second threshold voltage Vth2 of the positive polarity having an absolute value greater than the absolute value of the first threshold voltage Vth1 with respect to the read voltage of the positive polarity; the memory cell 130 has a second threshold voltage Vth2 of the positive polarity having an absolute value greater than the absolute value of the first threshold voltage Vth1 with respect to the read voltage of the positive polarity; the memory cell 130 has a third threshold voltage Vth3 of the positive polarity having an absolute value greater than the absolute value of the second threshold voltage Vth2 with respect to the read voltage of the positive polarity; the memory cell 130 has a fourth threshold voltage Vth4 of the positive polarity having an absolute value greater than the absolute value of the third threshold voltage Vth3 with respect to the read voltage of the positive polarity; see Figs.15-18, 20-21, 24-25, 27-28, Par.[0080], [0086], wherein this voltage VSL is a voltage for setting the selector portion 150 to the on-state and is greater than the threshold voltage Vth of the memory cell 130; when it becomes the time ton, the selector portion 150 enters the on-state and a current flows through the memory cell 130; this voltage −VSL is a voltage for setting the selector portion 150 to the on-state and an absolute value thereof is greater than the absolute value of the threshold voltage −Vth of the memory cell 130; when it becomes the time ton, the selector portion 150 enters the on-state and a current flows through the memory cell 130).
With respect to claim 11, Suzuki discloses, in Figs.1-28, the information reading method, wherein a level of the read voltage is about 80 % to about 95 % of a level of the set threshold voltage (see Fig.14 wherein, for example, level of VRD1/Vth2=2/3 or 66.66%; see Par.[0090] wherein it should be noted that although in the voltage applying operation shown in FIGS. 15 to 18, the absolute value of the voltage VSET of the positive polarity and absolute value of the voltage −VSET of the negative polarity are identical to each other, the absolute value of one of the above voltages may be within the range of 80% to 120% of the absolute value of the other of the voltages; likewise, although the absolute value of the voltage VRST of the positive polarity and absolute value of the voltage −VRST of the negative polarity are identical to each other, the absolute value of one of the above voltages may be within the range of 80% to 120% of the absolute value of the other of the voltages).
With respect to claim 12, Suzuki discloses, in Figs.1-28, the information reading method, wherein the reading reads the data value stored in the memory layer by measuring a value of change of a current flowing through the memory layer at the read voltage (see Par.[0096] wherein when the read voltage VRD1 is applied to the memory cell 130, if the memory cell 130 enters the on-state (if an on-current flows through the memory cell 130), the determining circuit 320 of FIG. 8 determines that the first data corresponding to the first memory state (low-resistance state/positive polarity state) is stored in the memory cell 130 (S12, S13); see Par.[0098] wherein When the read voltage VRD2 is applied to the memory cell 130, if the memory cell 130 enters the on-state (if an on-current flows through the memory cell 130), the determining circuit 320 of FIG. 8 determines that the second data corresponding to the second memory state (low-resistance state/negative polarity state) is stored in the memory cell 130 (S15, S16); see Par.[0101] wherein When the read voltage VRD3 is applied to the memory cell 130, if the memory cell 130 enters the on-state (if an on-current flows through the memory cell 130), the determining circuit 320 of FIG. 8 determines that the third data corresponding to the third memory state (high-resistance state/positive polarity state) is stored in the memory cell 130 (S19, S20)).
With respect to claim 13, Suzuki discloses, in Figs.1-28, the information reading method, wherein, when the value of change of the current measured in the memory layer is a relatively high value, the memory layer is read as set, and when the value of change of the current measured in the memory layer is a relatively low value, the memory layer is read as reset (see Par.[0081]-[0088] wherein FIG. 15 is a view showing a voltage applying operation at the time when the first memory state (low-resistance state/positive polarity state) is set to the memory cell 130; more specifically, FIG. 15 is a timing chart showing the voltage to be applied to the memory cell 130 and current flowing through the memory cell 130; FIG. 16 is a view showing a voltage applying operation at the time when the second memory state (low-resistance state/negative polarity state) is set to the memory cell 130. More specifically, FIG. 16 is a timing chart showing a voltage to be applied to the memory cell 130 and current flowing through the memory cell 130; FIG. 17 is a view showing a voltage applying operation at the time when the third memory state (high-resistance state/positive polarity state) is set to the memory cell 130. More specifically, FIG. 17 is a timing chart showing a voltage to be applied to the memory cell 130 and current flowing through the memory cell 130; FIG. 18 is a view showing a voltage applying operation at the time when the fourth memory state (high-resistance state/negative polarity state) is set to the memory cell 130. More specifically, FIG. 18 is a timing chart showing a voltage to be applied to the memory cell 130 and current flowing through the memory cell 130; see Par.[0115]-[0122] wherein First, as shown in FIG. 24 (a) the memory cell 130 enters the on-state (if an on-current flows through the memory cell 130), the determining circuit 320 of FIG. 8 determines that the first data corresponding to the first memory state (low-resistance state/positive polarity state) is stored in the memory cell 130 (S32, S33)).
With respect to claim 14, Suzuki discloses, in Figs.1-28, the information reading method, wherein a polarity of the read voltage is positive (+) (see Par.[0095]-[0098] wherein FIG. 21 is a timing chart showing a voltage applying operation at the time when a rewrite is carried out; the read voltage VRD1 having the positive polarity in (+); see Par.[0102]-[01111] wherein after applying the read voltage VRD3 of the positive polarity to the memory cell 130 as shown in FIG. 21 (b), a rewrite voltage of the positive polarity is applied to the memory cell 130; see Par.[0115]-[0119] wherein as shown in FIG. 24 (a) after applying the read voltage VRD3 of the positive polarity to the memory cell 130 as shown in FIG. 21 (b), a rewrite voltage of the positive polarity is applied to the memory cell 130).
With respect to claim 15, Suzuki discloses, in Figs.1-28, an information reading method of a self-selecting memory device, the self-selecting memory device including a first electrode, a second electrode, and a memory layer therebetween (see Par.[0043]-[0045] wherein the resistance change memory portion 140 has a structure in which the electrode 141, resistance change material layer 143, and electrode 142 are stacked in the Z-direction of FIG. 2), the memory layer including a chalcogenide-based material, having Ovonic threshold switching characteristics, and configured to have a threshold voltage that changes to a set threshold voltage or a reset threshold voltage higher than the set threshold voltage according to polarity and intensity of a voltage applied to the memory layer (see Par.[0058] wherein it is possible to further set, in addition to the two states (low-resistance state, high-resistance state) set to the resistance change memory portion 140, two states to the selector portion 150; see Par.[0068]-[0072] wherein it is possible to set the four states to the memory cell 130 and store the four-value data in the memory cell 130 on the basis of the two states (low-resistance state, high-resistance state) of the resistance change memory portion 140 and two states (positive polarity state, negative polarity state) of the selector portion 150; by setting the two states (low-resistance state, high-resistance state) to the resistance change memory portion 140 and by setting the two states (positive polarity state, negative polarity state) to the selector portion 150, it is possible to set the four states to the memory cell 130 and store the four-value data in the memory cell 130; it is submitted that Ovonic threshold switching is a phenomenon in certain chalcogenide materials where the material abruptly transitions from a high-resistance state to a low-resistance state when a threshold voltage is exceeded, enabling controlled current flow in memory devices), the information reading method comprising: reading a data value stored in the memory layer by sequentially applying, to the memory layer as a read voltage, rectangular pulse voltages whose levels gradually increase at a voltage lower than the set threshold voltage (see Par.[0073]-[0079] wherein the distribution (a) of FIG. 14 relates to the cases where: the memory cell 130 has a second threshold voltage Vth2 of the positive polarity having an absolute value greater than the absolute value of the first threshold voltage Vth1 with respect to the read voltage of the positive polarity; the memory cell 130 has a second threshold voltage Vth2 of the positive polarity having an absolute value greater than the absolute value of the first threshold voltage Vth1 with respect to the read voltage of the positive polarity; the memory cell 130 has a third threshold voltage Vth3 of the positive polarity having an absolute value greater than the absolute value of the second threshold voltage Vth2 with respect to the read voltage of the positive polarity; the memory cell 130 has a fourth threshold voltage Vth4 of the positive polarity having an absolute value greater than the absolute value of the third threshold voltage Vth3 with respect to the read voltage of the positive polarity; for rectangular pulse voltage see Figs.15-18, 20-21, 24-25, 27-28).
With respect to claim 16, Suzuki discloses, in Figs.1-28, the information reading method, wherein, when a certain pulse voltage applied to the memory layer is measured as the set threshold voltage, the memory layer is read as set, and when the certain pulse voltage applied to the memory layer is measured as the reset threshold voltage, the memory layer is read as reset (see Par.[0073]-[0079] wherein the distribution (a) of FIG. 14 relates to the cases where: the memory cell 130 has a second threshold voltage Vth2 of the positive polarity having an absolute value greater than the absolute value of the first threshold voltage Vth1 with respect to the read voltage of the positive polarity; the memory cell 130 has a second threshold voltage Vth2 of the positive polarity having an absolute value greater than the absolute value of the first threshold voltage Vth1 with respect to the read voltage of the positive polarity; the memory cell 130 has a third threshold voltage Vth3 of the positive polarity having an absolute value greater than the absolute value of the second threshold voltage Vth2 with respect to the read voltage of the positive polarity; the memory cell 130 has a fourth threshold voltage Vth4 of the positive polarity having an absolute value greater than the absolute value of the third threshold voltage Vth3 with respect to the read voltage of the positive polarity; for rectangular pulse voltage see Figs.15-18, 20-21, 24-25, 27-28).
Claims 1-9, 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (US 2022/0328104 A1 hereinafter referred to as “Lu”).
With respect to claim 1, Lu discloses, in Figs.1-6, an information reading method of a self-selecting memory device, the self-selecting memory device including a first electrode, a second electrode, and a memory layer therebetween (see Par.[0021] wherein the memory elements can include a storage element and a select element (e.g., a switching element) located between a pair of conductive lines (e.g., access lines, which may be referred to as word lines or select lines, and sense lines, which may be referred to as bit lines, data lines, or digit lines) such as in a cross-point configuration), the memory layer including a chalcogenide-based material, having Ovonic threshold switching characteristics, and configured to have a threshold voltage that changes to a set threshold voltage or a reset threshold voltage higher than the set threshold voltage according to polarity and intensity of a voltage applied to the memory layer (see Par.[0012] wherein memory cells exhibit ovonic threshold switching behavior, applying a read voltage (e.g., demarcation voltage Vdm) located at the center of the Vt distribution will generate a snapback event (e.g., ovonic threshold switching event) or not depending on whether the bouncing Vt of the cell is above or below the Vdm at the time of the read operation. As described further below, the resistance variable memory cells can comprise various chalcogenide materials among other materials exhibiting ovonic threshold switching behavior; see Par.[0021] wherein each memory cell may include a chalcogenide material that may be formed of various doped or undoped materials, that may or may not be a phase-change material, and/or that may or may not undergo a phase change during reading and/or writing the memory cell. Chalcogenide materials may be materials or alloys that include at least one of the elements S, Se, and Te. Chalcogenide materials may include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to, Ge—Te, In—Se, Sb—Te, Ga—Sb, In—Sb, As—Te, Al—Te, Ge—Sb—Te, Te—Ge—As, In—Sb—Te, Te—Sn—Se, Ge—Se—Ga, Bi—Se—Sb, Ga—Se—Te, Sn—Sb—Te, In—SbGe, Te—Ge—Sb—S, Te—Ge—Sn—O, Te—Ge—Sn—Au, Pd—Te—Ge—Sn, In—Se—Ti—Co, Ge—SbTe—Pd, Ge—Sb—Te—Co, Sb—Te—Bi—Se, Ag—In—Sb—Te, Ge—Sb—Se—Te, Ge—Sn—Sb—Te, GeTe—Sn—Ni, Ge—Te—Sn—Pd, or Ge— Te—Sn—Pt; see Par.[0075], [0080] wherein the second range of voltage values may have a normal distribution corresponding to the threshold voltage distribution for the second state in the memory cell; in some examples, the polarity associated with each state may be opposite to one another; see Par.[0080], [0083] wherein the pre-read operation 472 may involve applying a voltage from the center or midpoint of the threshold voltage distribution for that particular memory cell storing that particular reset state; in some examples including memory cells of an SSM device, the polarity of the threshold voltage distribution of the reset state and/or its mid-point may have an opposite polarity to the threshold voltage distribution of the set state and/or its mid-point; see Par.[0092], [0095], [0102] wherein the normal or typical programming sequence may involve programming the memory cell to, for example, the reset state by applying a programming pulse at a voltage at an appropriate level and/or polarity to program the memory cell to the reset state; the threshold voltage distribution for the reset state may have a negative polarity and/or a polarity opposite to that of the threshold voltage distribution of the set state), the information reading method comprising: reading a data value stored in the memory layer by applying, to the memory layer as a read voltage (Vdm), a voltage lower than the set threshold voltage (Vt) (see Par.[0024], [0028] wherein the Vdm (e.g., read voltage) can be a voltage level between the set and reset distributions in order to determine the state of cell; if the Vdm is greater than the Vt of the memory cell, then a snap back current is generated (e.g., a snap back event is detected) indicating that the cell is in the set state, and if the Vdm is less than the Vt of the memory cell, then a snap back current is not generated indicating the cell is in the reset state; see Par.[0070], [0077], [0096] wherein the first read voltage may be selected as a first read voltage that is within a predetermined threshold voltage distribution corresponding to the first state when the memory cell is programmed to a first state).
With respect to claim 2, Lu discloses, in Figs.1-6, the information reading method, wherein a level of the read voltage is about 40 % to about 90 % of a level of the set threshold voltage (see Par.[0036]-[0037] wherein fifty percent of the time the Vt for the memory cell programmed to the first state is above the center Vt value 252 and fifty percent of the time the Vt for the memory cell programmed to the first state is below the center Vt value 252; therefore, applying a voltage having the center Vt value 252 across the memory cell programmed to the second state will result in a snap back event fifty percent of the time and will not result in a snap back event fifty percent of the time).
With respect to claim 3, Lu discloses, in Figs.1-6, the information reading method, wherein the level of the read voltage is about 60 % to about 80 % of the level of the set threshold voltage (see Par.[0036]-[0037] wherein fifty percent of the time the Vt for the memory cell programmed to the first state is above the center Vt value 252 and fifty percent of the time the Vt for the memory cell programmed to the first state is below the center Vt value 252; therefore, applying a voltage having the center Vt value 252 across the memory cell programmed to the second state will result in a snap back event fifty percent of the time and will not result in a snap back event fifty percent of the time).
With respect to claim 4, Lu discloses, in Figs.1-6, the information reading method, wherein the reading reads the data value stored in the memory layer by measuring a current flowing through the memory layer at the read voltage (see Fig.3, Par.[0039], [0041]-[0042] wherein the horizontal axis represents an applied voltage and the vertical axis represents a current level; the horizontal axis includes a first threshold voltage level (VT1) 362 and a second threshold voltage level (VT2) 364; the Vdm voltage value 350 may correspond to Vdm 250 illustrated in FIG. 2 and may be located between the threshold voltage distributions 254-1 and 254-2 illustrated in FIG. 2. By applying the Vdm voltage value 350 in this intermediary point between VT1 and VT2, the presence of a snap back current would indicate that the memory cell being read has a Vt (e.g., VT1) below Vdm voltage value 350 and is in the set state. On the other hand, the absence of a snap back current when the Vdm voltage value 350 is applied would indicate that the memory cell being read has a Vt (e.g., VT2) above Vdm voltage value 350 and is in the reset state).
With respect to claim 5, Lu discloses, in Figs.1-6, the information reading method, wherein, when the current flowing through the memory layer is measured as a relatively high current value, the memory layer is read as set, and when the current flowing through the memory layer is measured as a relatively low current value, the memory layer is read as reset (see Par.[0023]-[0024], [0031]-[0034], [0040]-[0041] wherein the memory cells of memory 130 can be programmed to a particular state (e.g., set or reset) corresponding to a bit value (e.g., 1 or 0); as described further in association with FIGS. 2 and 3, the Vdm (e.g., read voltage) can be a voltage level between the set and reset distributions in order to determine the state of cell; if the Vdm is greater than the Vt of the memory cell, then a snap back current is generated (e.g., a snap back event is detected) indicating that the cell is in the set state, and if the Vdm is less than the Vt of the memory cell, then a snap back current is not generated indicating the cell is in the reset state).
With respect to claim 6, Lu discloses, in Figs.1-6, the information reading method, wherein the relatively high current value is 10 times or more the relatively low current value (see Par.[0031] wherein As an example, distribution 254-1 may be referred to as the set state, which can correspond to a low Vt state, and distribution 254-2 may be referred to as the reset state, which can correspond to a high Vt state (e.g., a state corresponding to relatively high Vt levels as compared to the Vt levels corresponding to the set state); see Par.[0042] wherein if the Vdm voltage value 350 is applied to the memory cell when the memory cell is programmed to the first state, a snap back event 366, illustrated as a rapid jump to higher current level, may occur since the VT1 voltage level is met and/or exceeded. However, if the Vdm voltage value 350 is applied to the memory cell when it is programmed to the second state, a snap back event 368, illustrated as a rapid jump to higher current level, may not occur since the VT2 voltage level is not met and/or exceeded; see Par.[0048]-[0049], [0053] wherein the normal or typical programming sequence may involve programming the memory cell to, for example, the reset state by applying a programming pulse at a voltage level higher than an uppermost reset Vt distribution in some examples such as a memory cell in 3D XPoint™ memory where the reset state is a high Vt state; the memory cell subjected to the pre-reading sequence 470 may include a memory cell in 3D XPoint™ memory pre-programmed to a first state such as a set state or low Vt state; the first pre-read operation 472 may be performed at a first read voltage that is within a predetermined threshold voltage distribution corresponding to the set or low Vt data state of a memory cell in 3D XPoint™ memory; see Par.[0036]-[0037] wherein fifty percent of the time the Vt for the memory cell programmed to the first state is above the center Vt value 252 and fifty percent of the time the Vt for the memory cell programmed to the first state is below the center Vt value 252; therefore, applying a voltage having the center Vt value 252 across the memory cell programmed to the second state will result in a snap back event fifty percent of the time and will not result in a snap back event fifty percent of the time).
With respect to claim 7, Lu discloses, in Figs.1-6, the information reading method, wherein a polarity of the read voltage is positive (+) (see Fig.4B).
With respect to claim 8, Lu discloses, in Figs.1-6, the information reading method, wherein the memory layer includes a chalcogen element including at least one of Se, Te, or S, and at least one of Ge, As, or Sb (see Par.[0021] wherein each memory cell may include a chalcogenide material that may be formed of various doped or undoped materials, that may or may not be a phase-change material, and/or that may or may not undergo a phase change during reading and/or writing the memory cell; Chalcogenide materials may be materials or alloys that include at least one of the elements S, Se, and Te. Chalcogenide materials may include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), platinum (Pt); example chalcogenide materials and alloys may include, but are not limited to, Ge—Te, In—Se, Sb—Te, Ga—Sb, In—Sb, As—Te, Al—Te, Ge—Sb—Te, Te—Ge—As, In—Sb—Te, Te—Sn—Se, Ge—Se—Ga, Bi—Se—Sb, Ga—Se—Te, Sn—Sb—Te, In—SbGe, Te—Ge—Sb—S, Te—Ge—Sn—O, Te—Ge—Sn—Au, Pd—Te—Ge—Sn, In—Se—Ti—Co, Ge—SbTe—Pd, Ge—Sb—Te—Co, Sb—Te—Bi—Se, Ag—In—Sb—Te, Ge—Sb—Se—Te, Ge—Sn—Sb—Te, GeTe—Sn—Ni, Ge—Te—Sn—Pd, or Ge— Te—Sn—Pt; see Par.[0075], [0080] wherein the second range of voltage values may have a normal distribution corresponding to the threshold voltage distribution for the second state in the memory cell; in some examples, the polarity associated with each state may be opposite to one another).
With respect to claim 9, Lu discloses, in Figs.1-6, the information reading method, wherein the memory layer further includes at least one of In, Al, C, B, Sr, Ga, O, N, Si, Ca, or P (see Par.[0021] wherein each memory cell may include a chalcogenide material that may be formed of various doped or undoped materials, that may or may not be a phase-change material, and/or that may or may not undergo a phase change during reading and/or writing the memory cell; Chalcogenide materials may be materials or alloys that include at least one of the elements S, Se, and Te. Chalcogenide materials may include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), platinum (Pt); example chalcogenide materials and alloys may include, but are not limited to, Ge—Te, In—Se, Sb—Te, Ga—Sb, In—Sb, As—Te, Al—Te, Ge—Sb—Te, Te—Ge—As, In—Sb—Te, Te—Sn—Se, Ge—Se—Ga, Bi—Se—Sb, Ga—Se—Te, Sn—Sb—Te, In—SbGe, Te—Ge—Sb—S, Te—Ge—Sn—O, Te—Ge—Sn—Au, Pd—Te—Ge—Sn, In—Se—Ti—Co, Ge—SbTe—Pd, Ge—Sb—Te—Co, Sb—Te—Bi—Se, Ag—In—Sb—Te, Ge—Sb—Se—Te, Ge—Sn—Sb—Te, GeTe—Sn—Ni, Ge—Te—Sn—Pd, or Ge— Te—Sn—Pt; see Par.[0075], [0080] wherein the second range of voltage values may have a normal distribution corresponding to the threshold voltage distribution for the second state in the memory cell; in some examples, the polarity associated with each state may be opposite to one another).
With respect to claim 15, Lu discloses, in Figs.1-6, an information reading method of a self-selecting memory device, the self-selecting memory device including a first electrode, a second electrode, and a memory layer therebetween (see Par.[0021] wherein the memory elements can include a storage element and a select element (e.g., a switching element) located between a pair of conductive lines (e.g., access lines, which may be referred to as word lines or select lines, and sense lines, which may be referred to as bit lines, data lines, or digit lines) such as in a cross-point configuration), the memory layer including a chalcogenide-based material, having Ovonic threshold switching characteristics, and configured to have a threshold voltage that changes to a set threshold voltage or a reset threshold voltage higher than the set threshold voltage according to polarity and intensity of a voltage applied to the memory layer (see Par.[0012] wherein memory cells exhibit ovonic threshold switching behavior, applying a read voltage (e.g., demarcation voltage Vdm) located at the center of the Vt distribution will generate a snapback event (e.g., ovonic threshold switching event) or not depending on whether the bouncing Vt of the cell is above or below the Vdm at the time of the read operation. As described further below, the resistance variable memory cells can comprise various chalcogenide materials among other materials exhibiting ovonic threshold switching behavior; see Par.[0021] wherein each memory cell may include a chalcogenide material that may be formed of various doped or undoped materials, that may or may not be a phase-change material, and/or that may or may not undergo a phase change during reading and/or writing the memory cell. Chalcogenide materials may be materials or alloys that include at least one of the elements S, Se, and Te. Chalcogenide materials may include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to, Ge—Te, In—Se, Sb—Te, Ga—Sb, In—Sb, As—Te, Al—Te, Ge—Sb—Te, Te—Ge—As, In—Sb—Te, Te—Sn—Se, Ge—Se—Ga, Bi—Se—Sb, Ga—Se—Te, Sn—Sb—Te, In—SbGe, Te—Ge—Sb—S, Te—Ge—Sn—O, Te—Ge—Sn—Au, Pd—Te—Ge—Sn, In—Se—Ti—Co, Ge—SbTe—Pd, Ge—Sb—Te—Co, Sb—Te—Bi—Se, Ag—In—Sb—Te, Ge—Sb—Se—Te, Ge—Sn—Sb—Te, GeTe—Sn—Ni, Ge—Te—Sn—Pd, or Ge— Te—Sn—Pt; see Par.[0075], [0080] wherein the second range of voltage values may have a normal distribution corresponding to the threshold voltage distribution for the second state in the memory cell; in some examples, the polarity associated with each state may be opposite to one another; see Par.[0080], [0083] wherein the pre-read operation 472 may involve applying a voltage from the center or midpoint of the threshold voltage distribution for that particular memory cell storing that particular reset state; in some examples including memory cells of an SSM device, the polarity of the threshold voltage distribution of the reset state and/or its mid-point may have an opposite polarity to the threshold voltage distribution of the set state and/or its mid-point; see Par.[0092], [0095], [0102] wherein the normal or typical programming sequence may involve programming the memory cell to, for example, the reset state by applying a programming pulse at a voltage at an appropriate level and/or polarity to program the memory cell to the reset state; the threshold voltage distribution for the reset state may have a negative polarity and/or a polarity opposite to that of the threshold voltage distribution of the set state), the information reading method comprising: reading a data value stored in the memory layer by sequentially applying, to the memory layer as a read voltage, rectangular pulse voltages whose levels gradually increase at a voltage lower than the set threshold voltage (see Par.[0024], [0028] wherein the Vdm (e.g., read voltage) can be a voltage level between the set and reset distributions in order to determine the state of cell; if the Vdm is greater than the Vt of the memory cell, then a snap back current is generated (e.g., a snap back event is detected) indicating that the cell is in the set state, and if the Vdm is less than the Vt of the memory cell, then a snap back current is not generated indicating the cell is in the reset state; see Par.[0070], [0077], [0096] wherein the first read voltage may be selected as a first read voltage that is within a predetermined threshold voltage distribution corresponding to the first state when the memory cell is programmed to a first state; see Par.[0048]-[0049] wherein the normal or typical programming sequence may involve programming the memory cell to, for example, the reset state by applying a programming pulse at a voltage level higher than an uppermost reset Vt distribution in some examples such as a memory cell in 3D XPoint™ memory where the reset state is a high Vt state; it may also mean that the memory cell has been pre-programmed to a known state with a write pulse; see Par.[0064] wherein if a snap back event is detected the controller may be configured to perform the programming operation 474 by causing a write pulse to be applied to the memory cell to write the memory cell from a set state to a reset state; see Par.[0086], [0092]-[0093] wherein if a snap back event is detected the controller may be configured to perform the programming operation 474 by causing a write pulse to be applied to the memory cell to write the memory cell from a set state to a reset state. If a snap back event is not detected, then the controller may be configured to forgo the programming operation 474 and leave the memory cell in the set state; see Figs.4A-4C for rectangular pulse voltage).
With respect to claim 16, Lu discloses, in Figs.1-6, the information reading method, wherein, when a certain pulse voltage applied to the memory layer is measured as the set threshold voltage, the memory layer is read as set, and when the certain pulse voltage applied to the memory layer is measured as the reset threshold voltage, the memory layer is read as reset (see Par.[0048]-[0049] wherein the normal or typical programming sequence may involve programming the memory cell to, for example, the reset state by applying a programming pulse at a voltage level higher than an uppermost reset Vt distribution in some examples such as a memory cell in 3D XPoint™ memory where the reset state is a high Vt state; it may also mean that the memory cell has been pre-programmed to a known state with a write pulse; see Par.[0064] wherein if a snap back event is detected the controller may be configured to perform the programming operation 474 by causing a write pulse to be applied to the memory cell to write the memory cell from a set state to a reset state; see Par.[0086], [0092]-[0093] wherein if a snap back event is detected the controller may be configured to perform the programming operation 474 by causing a write pulse to be applied to the memory cell to write the memory cell from a set state to a reset state. If a snap back event is not detected, then the controller may be configured to forgo the programming operation 474 and leave the memory cell in the set state; see Figs.4A-4C for rectangular pulse voltage).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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