DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Woo et al. (U.S. Patent Application Publication No. 2021/0384194).
Regarding to claim 1, Woo teaches a semiconductor device comprising:
lower electrodes on a substrate (Fig. 9, element BE, [0061], last 2 lines);
a support pattern between the lower electrodes (Fig. 9, element 112a, [0061], lines 2-3);
an upper electrode on the lower electrodes and the support pattern (Fig. 9, element TE, [0062], last 2 lines); and
a dielectric layer between the lower electrodes and the upper electrode, and between the support pattern and the upper electrode (Fig. 9, element DL, [0062], lines 1-2),
wherein the upper electrode comprises:
a first portion on upper surfaces of the lower electrodes (Fig. 9); and
a second portion on a sidewall of the support pattern (Fig. 9), and
wherein the first portion is thicker than the second portion (Fig. 9).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-11, and 20 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Han et al. (U.S. Patent Application Publication No. 2021/0210492).
Regarding to claim 1, Han teaches a semiconductor device comprising:
lower electrodes on a substrate (Fig. 4, Fig. 16I, element BE);
a support pattern between the lower electrodes (Fig. 4, Fig. 16I, element SL3/SL4);
an upper electrode on the lower electrodes and the support pattern (Fig. 4, Fig. 16I, element UE); and
a dielectric layer between the lower electrodes and the upper electrode, and between the support pattern and the upper electrode (Fig. 4, Fig. 16I, element DL),
wherein the upper electrode comprises:
a first portion on upper surfaces of the lower electrodes (Fig. 4, Fig. 16I); and
a second portion on a sidewall of the support pattern (Fig. 4, Fig. 16I), and
wherein the first portion is thicker than the second portion (Fig. 4, Fig. 16I).
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In the alternative, Han is silent as to the thickness dimensions in the specification. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the first portion to be thicker than the second portion in order to prevent cracking do to mismatch stress, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 2, Han teaches the second portion has a thickness that is about 50% to about 90% of a thickness of the first portion (Fig. 4, Fig. 16I).
Regarding to claim 3, Han does not disclose the first portion comprises a dent region having a concave shape adjacent to the second portion. However, it would have been an obvious matter of design choice to configure the first portion comprising a dent region having a concave shape adjacent to the second portion, since applicant has not disclosed that a den solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well without a den.
Regarding to claim 4, Han teaches
a mask insulating pattern on the first portion of the upper electrode opposite the lower electrodes (Fig. 16I, element 73); and
an interlayer insulating layer on the mask insulating pattern (Fig. 16I, element 48),
wherein the mask insulating pattern includes a material having etch selectivity with a material of the interlayer insulating layer ([0112], lines 4-5).
Regarding to claim 6, Han teaches the mask insulating pattern has a thickness smaller than a thickness of the first portion (Fig. 16I).
Regarding to claim 7, Han teaches the mask insulating pattern has a thickness smaller than a thickness of the second portion (Fig. 16I).
Regarding to claim 8, Han teaches the semiconductor device comprises a cell region (Fig. 4, left side) and a peripheral circuit region (Fig. 4, right side),
wherein the upper electrode is in the cell region (Fig. 4),
wherein the peripheral circuit region comprises a peripheral transistor and a peripheral contact plug electrically connected to the peripheral transistor (Fig. 4, element 56), and
wherein the second portion is between the peripheral contact plug and the support pattern (Fig. 4).
Regarding to claim 9, Han teaches a distance between the second portion and the peripheral contact plug is greater than a thickness of the first portion (Fig. 4).
Regarding to claim 10, Han teaches a metal layer on the first portion opposite the lower electrodes (Fig. 4, element MP).
Regarding to claim 11, Han teaches the semiconductor device comprises a cell region (Fig. 4, left side) and a peripheral circuit region (Fig. 4, right side),
wherein the upper electrode is in the cell region (Fig. 4),
wherein the peripheral circuit region comprises a peripheral transistor and a peripheral contact plug electrically connected to the peripheral transistor (Fig. 4, element 56), and
wherein the second portion is between the peripheral contact plug and the support pattern (Fig. 4).
Regarding to claim 20, Han teaches a semiconductor device, comprising:
active regions defined on a substrate by a device isolation layer, the active regions respectively comprising a first impurity region and a second impurity region (Fig. 4, element ACT, [0035], lines 1-4, lines 10-12);
word lines on the active regions and extending in a first direction (Fig. 4, element WL);
capping insulating patterns on top surfaces of the word lines, respectively (Fig. 4, element 10);
bit lines on the word lines and extending in a second direction intersecting the first direction (Fig. 4, element BL);
contact plugs between the bit lines and electrically connected to the second impurity region (Fig. 4, element 56/14); and
a capacitor on the contact plugs (Fig. 4, stack BE/DL/UE),
wherein the capacitor comprises:
lower electrodes on a substrate (Fig. 4, element BE);
a support pattern between the lower electrodes (Fig. 4, element SL3/SL4);
an upper electrode on the lower electrodes and the support pattern (Fig. 4, element UE); and
a dielectric layer between the lower electrodes and the upper electrode, and between the support pattern and the upper electrode (Fig. 4, element DL),
wherein the upper electrode comprises:
a first portion on upper surfaces of the lower electrodes (Fig. 4); and
a second portion on a sidewall of the support pattern (Fig. 4), and
wherein the first portion is thicker than the second portion (Fig. 4).
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In the alternative, Han is silent as to the thickness dimensions in the specification. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the first portion to be thicker than the second portion in order to prevent cracking do to mismatch stress, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claims 12-15 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (U.S. Patent Application Publication No. 2021/0210492).
Regarding to claim 12, Han teaches a semiconductor device comprising:
lower electrodes on a substrate (Fig. 4, Fig. 16I, element BE);
a support pattern between the lower electrodes (Fig. 4, Fig. 16I, element Sl3/SL4);
an upper electrode on the lower electrodes and the support pattern (Fig. 4, Fig. 16I, element UE);
a dielectric layer between the lower electrodes and the upper electrode, and between the support pattern and the upper electrode (Fig. 4, Fig. 16I, element DL); and
a mask insulating pattern on the upper electrode opposite the lower electrodes and the support pattern (Fig. 4, Fig. 16I, element 73),
wherein the upper electrode comprises:
a first portion on upper surfaces of the lower electrodes (Fig. 4, Fig. 16I); and
a second portion on a sidewall of the support pattern (Fig. 4, Fig. 16I).
Han is silent about the thickness dimensions. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the mask insulating pattern to be thinner than the first portion in order to enhance anisotropic etching profile, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 13, Han teaches the second portion has a thickness that is about 50% to about 90% of a thickness of the first portion (Fig. 4, Fig. 16I).
Regarding to claim 14, Han does not disclose the first portion comprises a dent region having a concave shape adjacent to the second portion. However, it would have been an obvious matter of design choice to configure the first portion comprising a dent region having a concave shape adjacent to the second portion, since applicant has not disclosed that a den solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well without a den.
Regarding to claim 15, Han teaches an interlayer insulating layer on the mask insulating pattern (Fig. 16I, element 48), wherein the mask insulating pattern includes a material having etch selectivity with a material of the interlayer insulating layer ([0112], lines 4-5).
Regarding to claim 17, Han teaches the mask insulating pattern has a thickness smaller than a thickness of the first portion (Fig. 16I).
Regarding to claim 18, Han teaches the semiconductor device comprises a cell region (Fig. 4, left side) and a peripheral circuit region (Fig. 4, right side),
wherein the upper electrode is in the cell region (Fig. 4),
wherein the peripheral circuit region comprises a peripheral transistor and a peripheral contact plug electrically connected to the peripheral transistor (Fig. 4, element 56), and
wherein the second portion is between the peripheral contact plug and the support pattern (Fig. 4).
Regarding to claim 19, Han teaches a distance between the second portion and the peripheral contact plug is greater than a thickness of the first portion and is greater than a thickness of the mask insulating pattern (Fig. 4).
Allowable Subject Matter
Claims 5 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 5, the prior art fails to anticipate or render obvious the claimed limitations including “the first portion comprises a dent region having a concave shape adjacent to the second portion, and wherein the dent region undercuts the mask insulating pattern” in combination with the limitations recited in claims 1 and 4.
Regarding to claim 16, the prior art fails to anticipate or render obvious the claimed limitations including “the first portion comprises a dent region having a concave shape adjacent to the second portion, and wherein the dent region undercuts the mask insulating pattern” in combination with the limitations recited in claim 12.
Pertinent Art
For the benefits of the Applicant, US-20200152584-A1, US-8614498-B2, US-11031460-B2, US-10332888-B2, US-10685877-B2, US-20210296322-A1, US-9437420-B2, and US-10468415-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to discloses “wherein the upper electrode comprises a first portion on upper surfaces of the lower electrodes; and a second portion on a sidewall of the support pattern, and wherein the mask insulating pattern is thinner than the first portion.”
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897
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