DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For independent claims 1 and 11, the limitation
“edge of the (first) gate cut structure to the (first) transistor semiconductor channel region”
Is considered indefinite, since the claim language does not limit what portion of channel region, the specific distance is drawn to. It appears from the Figs 1 and 2 that the distances d1/d2/d3/d4 are drawn from the (edge) of the gate cut structure to the (edge) of the channel region. For examination purposes this understanding is used to make the rejection below.
Appropriate correction/amendment is requested to fix the indefinite issue.
For independent claim 16, the limitation “gate cut structure have a substantially same width” renders the claim indefinite. For examination purposes, gate structure have a same width” understanding/interpretation is considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jun et al. (2025/0372384)
Regarding Claim 1, in Fig. 1A, Jun et al. discloses a semiconductor device comprising: a first transistor 101 (the left one) comprising a first transistor semiconductor channel region 108/104 and a first transistor gate 108/104 structure contacting the first transistor semiconductor channel region; a second transistor 101 (middle one) located adjacent to the first transistor and comprising a second transistor semiconductor channel region 108/104 and a second transistor gate structure 108/104 contacting the second transistor semiconductor channel region; and a third transistor 101 (the right one) located adjacent to the second transistor and comprising a third transistor semiconductor channel region 104/104 and a third transistor gate structure 108/104 contacting the third transistor semiconductor channel region; a first gate cut structure 120 (the left one) located between the first transistor and the second transistor; and a second gate cut structure 120 (the right one) located between the second transistor and the third transistor, wherein a first distance d from a first edge of the first gate cut structure to the first transistor semiconductor (edge of the) channel region is same as a second distance d from a second edge of the first gate cut structure to the second transistor semiconductor channel region, and a third distance d from a first edge of the second gate cut structure to the second transistor semiconductor channel region is same as a fourth distance d from a second edge of the second gate cut structure to the third transistor semiconductor channel region, and wherein the first distance, the second distance, the third distance and the fourth distance are equal to each other (see also Figs. 8A/8B, element 802, paragraphs 0025, 0032, 0038, 0060 and 0065)
Regarding Claim 2, the first gate cut structure 120 (left one) and the second gate cut structure 120 (the right one) have a same vertical height and each of the first gate cut structure and the second gate cut structure lands on a shallow trench isolation structure 106 that is located in a semiconductor device layer that is located beneath each of the first transistor 101 (left one), the second transistor 101 (middle one) and the third transistor 101 (right one).
Regarding Claim 3, the first gate cut structure 120 (left one, bottom portion) and the second gate structure (12 (the right one, top portion) have different widths.
Regarding Claim 4, the first gate cut structure 120 (left one, bottom portion) has a first vertical height and the second gate cut 120 (right one, top portion) structure have a second vertical height, wherein the second vertical height differs from the first vertical height.
Regarding Claim 5, the first gate cut structure 120 (left one, bottom portion) and the second gate structure 120 (right one, top portion) have different widths.
Regarding Claim 6, the first vertical height of the first gate cut structure 120 (left one, bottom portion) is less than the second vertical height of the second gate cut structure 120 (right one, top portion), and the first transistor gate structure 101 (left one) and the second transistor gate structure 101 (middle one) merge under the first gate cut structure, and the second gate cut structure 120 (right one) lands on a shallow trench isolation structure 106 that is located in a semiconductor device layer 106 that is located beneath each of the first transistor 101 (left), second transistor 101 (middle) and third transistor 101 (right).
Regarding Claim 7, the first transistor gate structure 101 (left one) and the second transistor gate structure 101 (middle one) are composed of a compositionally same gate dielectric material and gate electrode.
Regarding Claim 8, at least one of the first gate cut structure 120 (left one) or the second gate cut structure 120 (right one) lands on a surface of a backside gate cut structure, and the backside gate cut structure is in contact with a backside power distribution network (see paragraph 0035).
Regarding Claim 9, a combined frontside middle-of-the-line/back-end-of-the-line structure located above the first transistor 101 (left one), the second transistor 101 (middle one), and the third transistor 101 (right one), and the combined frontside middle-of-the-line/back-end-of-the-line structure is electrically connected to each of the first transistor, the second transistor, and the third transistor via frontside gate contact structures (see paragraphs 0035 and 0073)
Regarding Claim 10, each of the first transistor semiconductor channel region 104/116, the second transistor semiconductor channel region 104/116, and the third transistor semiconductor channel region 104/116 is a vertical stack of spaced apart semiconductor channel material nanosheets.
Regarding Claim 11, in Fig. 1A along with Figs. 8A/8B, element 802, paragraphs 0025, 0032, 0038, 0060 and 0065, Jun et al. discloses a semiconductor device comprising: a first transistor 101 (left one) comprising a first transistor semiconductor channel region 104/116 and a first transistor gate structure contacting the first transistor semiconductor channel region; a second transistor 101 (middle one) located adjacent to the first transistor and comprising a second transistor semiconductor channel region 104/116 and a second transistor gate structure contacting the second transistor semiconductor channel region; and a third transistor 101 (right one) located adjacent to the second transistor and comprising a third transistor semiconductor channel region 104/116 and a third transistor gate structure contacting the third transistor semiconductor channel region; a first gate cut 120 structure 120 (left one) located between the first transistor and the second transistor; and a second gate cut structure 120 (right one) located between the second transistor and the third transistor, wherein a first distance d from a first edge of the first gate cut structure to the first transistor semiconductor channel region is same as a second distance d from a second edge of the first gate cut structure to the second transistor semiconductor channel region, and a third distance d from a first edge of the second gate cut structure to the second transistor semiconductor channel region is same as a fourth distance from a second edge of the second gate cut structure to the third transistor semiconductor channel region, and wherein the first distance, the second distance, the third distance and the fourth distance are equal to each other, and further wherein the first transistor gate structure extends beneath the first gate cut structure and contacts the second transistor gate structure, and the second gate cut structure lands on a shallow trench isolation structure 106 that is located in a semiconductor device layer 102 that is located beneath each of the first transistor 101 (left one), second transistor 101 (middle one) and third transistor 101 (right one).
Regarding Claim 12, the first transistor gate structure 104/116 is compositionally different from the second transistor gate structure 104/116 (see paragraphs 0036, 0038, 0040 and 0041).
Regarding Claim 13, the first transistor gate structure 101 is of a different conductivity type than the second transistor gate structure 101 (see paragraphs 0041, 0068 and 0087)
Regarding Claim 14, a combined frontside middle-of-the-line/back-end-of-the-line structure located above the first transistor, the second transistor, and the third transistor, and the combined frontside middle-of-the-line/back-end-of-the-line structure is electrically connected to each of the first transistor, the second transistor, and the third transistor via frontside gate contact structures (see paragraphs 0035 and 0073).
Regarding Claim 15, each of the first transistor semiconductor channel region 104/116, the second transistor semiconductor channel region 104/116, and the third transistor semiconductor channel region 104/116 is a vertical stack of spaced apart semiconductor channel material nanosheets.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Reboh et al. (20250212508) .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding Claim 16, in Figs. 2A, 4A, 5A, 6A, 8A and 17A, Reboh et al. discloses a semiconductor device comprising: a first FET stack comprising a fourth transistor 1701 stacked above a first transistor; a second FET stack located adjacent to the first FET stack and comprising a fifth transistor 1701 stacked above a second transistor; a third FET stack located adjacent to the second FET stack and comprising a sixth transistor 1701 stacked above a third transistor, wherein each of the first transistor, the second transistor and the third transistor comprises a first semiconductor channel region 1342 of a first channel length and each of the fourth transistor, the fifth transistor and the sixth transistor comprises a second semiconductor channel region 1342 of a second channel length that is less than the first channel length; a first gate cut structure 158 located between the first transistor and the second transistor; a second gate cut structure 158 located between the second transistor and the third transistor; a third gate cut structure located between the fourth transistor and the fifth transistor and in contact with the first gate cut structure; and a fourth gate cut structure located between the fifth transistor and the sixth transistor and in contact with the second gate cut structure, wherein the first gate cut structure 158 and the third gate cut structure 158 have a substantially same width, and the fourth gate cut structure 158 has a width that is greater than a width of the second gate cut structure.
Regarding Claim 17,a first distance from the first gate cut structure 158 to each of the first semiconductor channel region of the first transistor is equal to a second distance from the first gate cut structure to the second semiconductor channel region of the second transistor, and a third distance from the second gate cut structure to the first semiconductor channel region of the second transistor is equal to a fourth distance from the second gate cut structure to the first semiconductor channel region of the third transistor, and a fifth distance from the third gate cut structure to the second semiconductor channel region of the fourth transistor is equal to a sixth distance from the third gate cut structure to each of the second semiconductor channel regions of the fifth transistor, a seventh distance from the fourth gate cut structure to each of the second semiconductor channel region of the fifth transistor is equal to an eighth distance from the fourth gate cut structure to each of the second semiconductor channel region of the sixth transistor, and wherein the first distance, the second distance, the third distance, the fourth distance, the fifth distance, the sixth distance, the seventh distance and the eighth distance are equal to each other (see paragraphs 0080, 0111, 0125)
Regarding Claim 18, each of the first gate cut structure 158 and the second gate cut structure 158 lands on a backside gate cut structure that is present in a semiconductor device layer that is located beneath of the first FET stack, the second FET stack and the third FET stack (see paragraphs 0125, 0163, 0164, 0168)
Regarding Claim 19, in paragraphs 0125, 0163, 0164 and 0168, a backside power distribution network structure located beneath the semiconductor device layer and in contact with each of the backside gate cut structures.
Regarding Claim 20, in paragraphs 0144, 0163 and 016 a combined frontside middle-of-the-line/back-end-of-the-line structure located above the first FET stack, the second FET stack and the third FET stack.
Examiner is including Lilak 20220115372 (Fig. 4) as pertinent prior art reference that is NOT relied upon for this rejection but that discloses stacked nanosheet FET transistors with gate cut/conductor between the lower and upper stacks with distances from the gate cut/conductor to the nanosheet channels
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 7/8/2026
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