DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
The IDS document(s) filed on July 9, 2024 has been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Specifications
The title is objected to because a more descriptive title is requested.
Claim Objections
As to claim 24, the Examiner suggests “a second wiring that has
Claim Rejections – 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. § 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 15-26 are rejected under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention.
As to claim 15, there is a lack of antecedent basis for “the multi-layer second wiring layer” (emphasis added). The Examiner suggests “the second multi-layer
As to claims 20 and 25, the Examiner suggests “the llaminated body” to maintain antecedent basis with parent claim 1.
Nonstatutory Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 15-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, and 5 of U.S. Patent No. 11,289,525 B2 in view of Kobayashi et al. (U.S. Patent Publication No. 2012/0062777 A1), as cited in the IDS and hereafter “Kobayashi”.
Claims of U.S. Patent No. 11,289,525 B2
Claims of the Instant Application
(Claim 1) A solid-state imaging device, comprising: a pixel region that includes a plurality of pixels;
a first wiring in a first layer;
a second wiring in a second layer, wherein the second layer is lower than the first layer;
a first shield layer between the first wiring in the first layer and the second wiring in the second layer;
a laminated body that includes a first semiconductor substrate as an uppermost layer and a second semiconductor substrate; and a second shield layer in the first semiconductor substrate, wherein the first semiconductor substrate includes the pixel region and the first wiring, the second semiconductor substrate includes the second wiring and a logic circuit, the first shield layer is, above the second wiring, in the second semiconductor substrate, a potential associated with the first shield layer is a fixed potential, the second shield layer is connected to a ground wiring of the first semiconductor substrate through a first plurality of via holes, the first semiconductor substrate has a connection conductor connected to the first wiring, and the connection conductor is in contact with the second wiring of the second semiconductor substrate.
However, the ‘525 Patent does not teach the connection conductor comprises a plurality of connection conductors nor the first and second wirings being multi-layer wirings.
On the other hand, Kobayashi teaches a plurality of connection conductors 68 and first and second multi-layer wirings 41, 55. See Kobayashi, FIG. 3.
It would have been obvious to one of ordinary skill in the art before the effective filing date to substitute Kobayashi’s plurality of connector conductors and multi-layer wirings for the ’525 Patent’s single structures in order to yield the predictable benefit of electrically connecting the first and second semiconductor substrates and different transistor structures, respectively. Id. at ¶¶ [0067], [0070], [0072].
(Claim 15) A solid-state imaging device, comprising:
a laminated body that includes: a first semiconductor wafer including a pixel region and a first multi-layer wiring layer;
a second semiconductor wafer including a logic circuit and a second multi-layer wiring layer;
a shield layer between the first multi-layer wiring layer and the multi-layer second wiring layer, wherein the shield layer is electrically connected to a fixed potential;
and a plurality of connection conductors configured to electrically connect the first semiconductor wafer to the second semiconductor wafer.
1
16
1
17
2
18
5
19
Kobayashi teaches an insulation film 67 that covers a periphery of the plurality of connection conductors 68.
20
Prior Art Not Relied Upon
The following prior art was not relied upon but is made of record:
Yang et al. (U.S. Patent Publication No. 2012/0061789 A1)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUBERR L CHI/Primary Examiner, Art Unit 2893
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