DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to RCE filed on 02/25/2026. Claim 4 was canceled before. Claims 1-3 and 5-11 have been examined and are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/25/2026 has been entered.
Response to Arguments
Applicant's arguments filed 02/25/2026 have been fully considered but they are not persuasive.
Applicant argues, page 7 of the remarks, “Shen does not teach specifying a first range value and a second range value in the NAND memory where an error has occurred.”
The Examiner respectfully disagrees. The Examiner submits that Shen teaches, referring to FIG. 3, “At operation 320, the processing logic causes a read operation to be performed at a subset of the group of manage units. The subset of the group of managed units can be, for example, a small sampling of managed units such as five percent (or ten percent) of the managed units that make up the group of managed units.” [0047] of Shen. Further, “At operation 330, the processing logic determines a bit error rate (e.g., RBER) related to data read from the subset of the group of managed units.” [0048] of Shen. “If, at operation 335, the bit error rate satisfies the threshold criterion, at operation 340, the processing logic causes a rewrite [refresh] of the data stored at the group of managed units, e.g., at each managed unit of the group of managed units. If, at operation 335, the bit error rate does not satisfy the threshold criterion, at operation 350, the processing logic refrains from rewriting data stored at the group of managed units.” [0050] of Shen.
Shen further teaches “For example, the processing logic can cause a read operation to be performed at a second subset of a second group of managed units, e.g. during another time through the operations 315 through 335. The processing logic can further determine a second bit error rate related to data read from the second subset of the second group of managed units. The processing logic can further, in response to the second bit error rate not satisfying the threshold criterion, refrain from rewriting data stored at the second group of managed units.” [0051] of Shen.
Therefore, Shen teaches all of the claim limitations of independent claim 1.
In view of the foregoing remarks, independent claim 1 is not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-8, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. US 2023/0044318 (“Shen”).
As per independent claim 1, Shen teaches A NAND storage device (“The memory sub-system 110 can include media, such as … one or more non-volatile memory devices (e.g., memory device 130),” para 0020 and FIG. 1A. “non-volatile memory devices (e.g., memory device 130) include negative-and (NAND) type flash memory” para 0025) comprising:
a NAND memory which is installed in the NAND storage device (“non-volatile memory devices (e.g., memory device 130) include negative-and (NAND) type flash memory” para 0025) and includes a first memory area and a second memory area (“a memory sub-system controller can perform media management operations (e.g., wear level operations, refresh operations, etc.) on SMUs [Super Managed Units].” Para 0011);
a built-in controller which is installed in the NAND storage device and works to write or read data in or from the NAND memory in response to a command outputted from an external device (“The memory sub-system controller 115 can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130 and other such operations.” Para 0028 and FIG. 1A),
wherein the built-in controller obtains a first refresh threshold (“for a first directional error rate (e.g., RBER.sub.01), the particular threshold voltage direction is in a direction of decreasing threshold voltage.” Para 0041) and a second refresh threshold (“for a second directional error rate (e.g., RBER.sub.10), the particular threshold voltage direction is in a direction of increasing threshold voltage.” Para 0041), the built-in controller working to compare a bit error rate in the first memory area of the NAND memory with the first refresh threshold to determine whether it is required to self-refresh data in the first memory area (“If, at operation 335, the bit error rate satisfies the threshold criterion, at operation 340, the processing logic causes a rewrite of the data stored at the group of managed units, e.g., at each managed unit of the group of managed units. If, at operation 335, the bit error rate does not satisfy the threshold criterion, at operation 350, the processing logic refrains from rewriting data stored at the group of managed units. In one embodiment, to “refrain from” is to “not perform” the re-write on a particular SMU.” Para 0050 and FIG. 3) and also compare a bit error rate in the second memory area of the NAND memory with the second refresh threshold to determine whether it is required to self-refresh data in the second memory area (“the processing logic can cause a read operation to be performed at a second subset of a second group of managed units, e.g. during another time through the operations 315 through 335. The processing logic can further determine a second bit error rate related to data read from the second subset of the second group of managed units. The processing logic can further, in response to the second bit error rate not satisfying the threshold criterion, refrain from rewriting data stored at the second group of managed units.” Para 0051 and FIG. 3),
the built-in controller is configured to compare: the bit error rate in the first memory area specified by the first range value with the first refresh threshold to determine whether the data in the first memory area is required to be self-refreshed (“If, at operation 335, the bit error rate satisfies the threshold criterion, at operation 340, the processing logic causes a rewrite of the data stored at the group of managed units, e.g., at each managed unit of the group of managed units. If, at operation 335, the bit error rate does not satisfy the threshold criterion, at operation 350, the processing logic refrains from rewriting data stored at the group of managed units. In one embodiment, to “refrain from” is to “not perform” the re-write on a particular SMU.” Para 0050 and FIG. 3) and the bit error rate in the second memory area specified by the second range value with the second refresh threshold to determine whether the data in the second memory area is required to be self-refreshed (“The processing logic can further determine a second bit error rate related to data read from the second subset of the second group of managed units. The processing logic can further, in response to the second bit error rate not satisfying the threshold criterion, refrain from rewriting data stored at the second group of managed units.” Para 0051).
Shen does not explicitly teach specifying a first range value and a second range value. The first range value and the second range value are mapped to the managed units of Shen. In view of this mapping, Shen teaches wherein the built-in controller specifies a first range value and a second range value in the NAND memory where an error has occurred (“At operation 330, the processing logic determines a bit error rate (e.g., RBER) related to data read from the subset of the group of managed units.” [0048]. “The processing logic can further determine a second bit error rate related to data read from the second subset of the second group of managed units.” [0051]), the first range value specifying a range occupied by the first memory area in the NAND memory where the error has occurred (“At operation 330, the processing logic determines a bit error rate (e.g., RBER) related to data read from the subset of the group of managed units.” [0048]), the second range value specifying a range occupied by the second memory area in the NAND memory where the error has occurred (“The processing logic can further determine a second bit error rate related to data read from the second subset of the second group of managed units.” [0051]).
Given the teaching of Shen, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Shen with “wherein the built-in controller specifies a first range value and a second range value in the NAND memory where an error has occurred, the first range value specifying a range occupied by the first memory area in the NAND memory where the error has occurred, the second range value specifying a range occupied by the second memory area in the NAND memory where the error has occurred”. The motivation would be that the present discloses lengthens the lifetime of a memory device by avoiding unnecessary power-on scrubbing, para 0019 of Shen.
As per dependent claim 7, Shen discloses the device of claim 1. Shen teaches wherein the first memory area stores therein a program to be executed by the external device, the second memory area stores therein a map data used by the external device when executing the program (“address translations between a logical address (e.g., logical block address (LBA, namespace) and a physical address (e.g., physical MU address, physical block address) that are associated with the memory devices 130.” Para 0031), the second refresh threshold is greater than first refresh threshold (“for a second directional error rate (e.g., RBER.sub.10), the particular threshold voltage direction is in a direction of increasing threshold voltage.” Para 0041).
As per dependent claim 8, Shen discloses the device of claim 7. Shen teaches wherein the second memory area stores therein a temporary update data for update of the program or the map data (“address translations between a logical address (e.g., logical block address (LBA, namespace) and a physical address (e.g., physical MU address, physical block address) that are associated with the memory devices 130.” Para 0031).
As per dependent claim 11, Shen discloses the device of claim 1. Shen teaches wherein the NAND storage device is installed in a vehicle (“The host system 120 can be a computing device such as a desktop computer, laptop computer, network server, mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance),” para 0023).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of Mokhlesi US 2014/0198567 (“Mokhlesi”).
As per dependent claim 2, Shen discloses the device of claim 1. Shen may not explicitly disclose, but in an analogous art in the same field of endeavor, Mokhlesi teaches wherein at least one of the first refresh threshold and the second refresh threshold is capable of being modified in response to a command outputted from the external device (“the controller issues a command to the state machine to update the read compare points.” Para 0110 and FIG. 18C).
Given the teaching of Mokhlesi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Shen with “wherein at least one of the first refresh threshold and the second refresh threshold is capable of being modified in response to a command outputted from the external device”. The motivation would be that the invention reduces the likelihood of error during reading data from non-volatile memory, para 0008 of Mokhlesi.
As per dependent claim 3, Shen discloses the device of claim 1. Shen teaches wherein the NAND memory stores therein a program to be executed by the external device or a map data used in the external device (“address translations between a logical address (e.g., logical block address (LBA, namespace) and a physical address (e.g., physical MU address, physical block address) that are associated with the memory devices 130.” Para 0031).
Shen may not explicitly disclose, but in an analogous art in the same field of endeavor, Mokhlesi teaches at least one of the first refresh threshold and the second refresh threshold is capable of being altered in response to a command from the external device when the program or the map data is updated (“After programming the neighbor memory cell, the floating gate to floating gate coupling effect may raise the apparent threshold voltage of earlier programmed memory cell.” Para 0064. “the controller issues a command to the state machine to update the read compare points.” Para 0110 and FIG. 18C).
Given the teaching of Mokhlesi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Shen with “at least one of the first refresh threshold and the second refresh threshold is capable of being altered in response to a command from the external device when the program or the map data is updated”. The motivation would be that the invention reduces the likelihood of error during reading data from non-volatile memory, para 0008 of Mokhlesi.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of Merry et al. US 8,127,048 (“Merry”).
As per dependent claim 5, Shen discloses the device of claim 4. Shen may not explicitly disclose, but in an analogous art in the same field of endeavor, Merry teaches wherein at least one of the first range value and the second range value is capable of being altered in response to a command outputted from the external device (“The user uses a series of vendor-specific commands to define the number of zones, size of each zone (e.g., beginning and ending PBAs),” col 5 line 66 to col 6 line 1).
Given the teaching of Merry, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Shen with “wherein at least one of the first range value and the second range value is capable of being altered in response to a command outputted from the external device”. The motivation would be that the invention permits setting separate access parameters for different zones, col 1 lines 49-51 of Merry, and as a result improves security.
As per dependent claim 6, Shen discloses the device of claim 4. Shen teaches wherein the NAND memory stores therein a program to be executed by the external device or a map data used in the external device (“address translations between a logical address (e.g., logical block address (LBA, namespace) and a physical address (e.g., physical MU address, physical block address) that are associated with the memory devices 130.” Para 0031).
Shen may not explicitly disclose, but in an analogous art in the same field of endeavor, Merry teaches at least one of the first range value and the second range value is capable of being altered in response to a command outputted from the external device when the program or the map data is updated (“The user uses a series of vendor-specific commands to define the number of zones, size of each zone (e.g., beginning and ending PBAs),” col 5 line 66 to col 6 line 1).
Given the teaching of Merry, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Shen with “at least one of the first range value and the second range value is capable of being altered in response to a command outputted from the external device when the program or the map data is updated”. The motivation would be that the invention permits setting separate access parameters for different zones, col 1 lines 49-51 of Merry, and as a result improves security.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of Bazarsky et al. US 2020/0401850 (“Bazarsky”).
As per dependent claim 9, Shen discloses the device of claim 7. Shen may not explicitly disclose, but in an analogous art in the same field of endeavor, Bazarsky teaches wherein the first memory area stores therein dynamic learning data which is read or modified when the external device executes the program (“FIG. 1 is a block diagram of a … SSD having an NVM with on-chip machine learning data” para 0031 and FIG. 1).
Given the teaching of Bazarsky, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Shen with “wherein the first memory area stores therein dynamic learning data which is read or modified when the external device executes the program”. The motivation would be that the invention allows increasing the size of the training data set, para 0003 of Bazarsky, and as a result improves on storage flexibility.
As per dependent claim 10, Shen discloses the device of claim 1. Shen teaches the second refresh threshold is greater than the first refresh threshold (“for a second directional error rate (e.g., RBER.sub.10), the particular threshold voltage direction is in a direction of increasing threshold voltage.” Para 0041).
Shen may not explicitly disclose, but in an analogous art in the same field of endeavor, Bazarsky teaches wherein the data retained in the second memory area has a size greater than that of the data retained in the first memory area (“stores the labeled images within a first portion or first region 406 … stores the augmented set of images … into a second region or second portion 414” para 0045 and FIG. 4),
and a ratio of a capacity of the first memory area to the size of the data in the first memory area is greater than a ratio of a capacity of the second memory area to the size of the data in the second memory area (“stores the labeled images within a first portion or first region 406 … stores the augmented set of images … into a second region or second portion 414” para 0045 and FIG. 4).
Given the teaching of Bazarsky, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Shen with “wherein the data retained in the second memory area has a size greater than that of the data retained in the first memory area” and “and a ratio of a capacity of the first memory area to the size of the data in the first memory area is greater than a ratio of a capacity of the second memory area to the size of the data in the second memory area”. The motivation would be that the invention allows increasing the size of the training data set, para 0003 of Bazarsky, and as a result improves on storage flexibility.
Conclusion
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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