DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation “the upper surface of the upper redistribution layer” in second and third lines of the claim. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner interprets “the upper surface of the upper redistribution layer” as “an upper surface of the upper redistribution layer”.
Claim 15 recites the limitation “the upper surface of the upper redistribution layer” in third line of the claim. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner interprets “the upper surface of the upper redistribution layer” as “an upper surface of the upper redistribution layer”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2014/0203429 A1, hereinafter Yu ‘429).
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With respect to Claim 1 Yu ‘429 discloses an integrated circuit package (Fig 1-8) comprising:
a redistribution layer (45, Fig 8, Para [0015]);
a logic die (24, Fig 8, Para [0009] discloses 24 as a logic die) coupled to a first surface (top surface 45 as shown in annotated Fig 8 of Yu ‘429, hereinafter FS) of the redistribution layer (45) through a first plurality of interconnects (26 on 24 as shown in annotated Fig 8 of Yu ‘429, Para [0011]); and
a plurality of memory dies (plurality of 324, Fig 8, Para [0010]) arranged into a stack (124 disclosed in Fig 8 and Para [0010]), the plurality of memory dies (plurality of 324) coupled to the first surface (FS) of the redistribution layer (45) through a second plurality of interconnects (26 on plurality of 324 as shown in annotated Fig 8 of Yu ‘429)( plurality of 324 coupled to first surface of 45 disclosed in Fig 8).
With respect to Claim 2 Yu ‘429 discloses all limitations of the integrated circuit package of claim 1, and Yu ‘429 further discloses wherein an active surface (bottom of 24 as shown in annotated Fig 8 of Yu ‘429) of the logic die (24) faces the first surface (FS) of the redistribution layer (45)(Para [0011] discloses connectors 26 electrically connect to 24 on the bottom of 24, therefore the active surface of 24).
Claims 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2024/0136272 A1, hereinafter Lee ‘272).
With respect to Claim 10 Lee ‘272 discloses an integrated circuit package (Fig 1-4B and 7), comprising:
an upper redistribution layer (210, Fig 7, Para [0065]);
at least one stack of memory dies (stack of 220, Fig 7, Para [0066] discloses 220 as a memory chip);
a plurality of wire bonds (WB, Fig 7, Para [0066]) coupled between the at least one stack (stack of 220) and the upper redistribution layer (210)(Fig 7 and Para [0066] disclose WB couple stack of 220 and 210);
a lower redistribution layer (110, Fig 7, Para [0020]) coupled to the upper redistribution (210) layer through a plurality of through-mold vias (130, Fig 7, Para [0040 and 0067 disclose 130 couple to RDL 210);
a logic die (120, Fig 7, Para [0038] disclose 120 as a logic die); and
a plurality of interconnects (123, Fig 7, Para [0039]) coupled between an active surface (lower surface of 120, Fig 7, Para [0060] discloses the lower surface of 120 is the active surface) of the logic die (120) and an upper surface (top of RDL 110 as shown in Fig 7) of the lower redistribution layer (110).
With respect to Claim 11 Lee ‘272 discloses all limitations of the integrated circuit package of claim 10, and Lee ‘272 further discloses wherein the plurality of interconnects (123) comprises a plurality of metal pillars (121, Fig. 7, Para [0039] discloses 123 comprising pillars 121).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yu ‘429 in view of Bao et al. (US 2022/0310480 A1, hereinafter Bao ‘480) in view of the following arguments.
With respect to Claim 3 Yu ‘429 discloses all limitations of the integrated circuit package of claim 2, but Yu ‘429 fails to explicitly disclose wherein the first plurality of interconnects comprises a plurality of micro bumps.
Nevertheless, in a related endeavor (Fig 1-25 of Bao ‘480), Bao ‘480 teaches wherein the first plurality of interconnects (128, Fig 5 of Bao ‘480, Para [0031]) comprises a plurality of micro bumps (Para [0031] discloses 128 as micro bumps).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Bao ‘480’s teaching of wherein the first plurality of interconnects comprises a plurality of micro bumps into Yu ‘429’s device. Yu ‘429 teaches a logic die and memory die stack on a redistribution layer and further teaches the use of metal pillars to connect the logic die to the redistribution layer. Bao ‘480 teaches a memory die over a logic die and teaches the logic die connected to the redistribution layer comprises micro bumps. One of ordinary skill in the art would recognize that metal pillars and micro bumps are well-known methods to achieve the predictable result of creating an electrical connection between a chip and a redistribution layer. A person of ordinary skill in the art would therefore have a reasonable expectation of success in substituting the well-known element of micro bumps for the well-known element of metal pillar connections. Therefore it would be obvious to the ordinary artisan make the simple substitution of micro bumps as the first plurality of interconnects. (MPEP 2143 (I)(B)).
As incorporated, the micro bumps (128) taught by Bao ‘480 as the first plurality of interconnects (26 on 24) of Yu ‘429.
With respect to Claim 4 Yu ‘429 as modified by Bao ‘480 discloses all limitations of the integrated circuit package of claim 3, and Bao ‘480 further discloses wherein the plurality of micro bumps (128) comprises a plurality of copper micro bumps (Para [0031] discloses 128 as micro bumps formed from copper).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yu ‘429 in view of Kyung et al. (US 2024/0170456 A1, hereinafter Kyung ‘456) in view of the following arguments.
With respect to Claim 5 Yu ‘429 discloses all limitations of the integrated circuit package of claim 1, but Yu ‘429 wherein each memory die comprises a dynamic random-access memory die having an active surface facing away from the first surface of the redistribution layer.
Nevertheless, in a related endeavor (Fig 14-15 of Kyung ‘456), Kyung ‘456 teaches wherein each memory die (320/330/340, Fig 15 of Kyung ‘456, Para [0032]) comprises a dynamic random-access memory die (Para [0032] of Kyung ‘456 discloses 320/330/340 as DRAM) having an active surface (tops of 320/330/340 as shown in Fig 15 of Kyung ‘456 and Para [0041] of Kyung ‘456 discloses wire connections electrically connect to tops of 320/330/340, therefore the active surface of 24) facing away from the first surface (top of 100 as shown in Fig 15 of Kyung ‘456) of the redistribution layer (100, Fig 15 of Kyung ‘456, Para [0027 and 0030]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Kyung ‘456’s teaching of wherein each memory die comprises a dynamic random-access memory die having an active surface facing away from the first surface of the redistribution layer into Yu ‘429’s device. Yu ‘429 discloses a semiconductor package comprising a logic die and a memory stack on a redistribution layer. Kyung ‘456 a teaches a semiconductor package comprising a logic and a stack of memory dies on a redistribution layer and in an embodiment teaches the stack of memory dies with active faces away from the redistribution layer. Further Yu ‘429 discloses (Para 0020) the memory stack generates heat. Kyung ‘456 teaches (Para 0091) that shifting the alignment of the stacked chips can improve reliability in an environment where chip bending can occur due to temperature (“even if bending of the stack structure of the semiconductor chips occurs in a cooling environment, damage applied to the upper pad can be reduced by reducing the repulsive force by the lower pad”). The ordinary artisan would have been motivated to modify Yu ‘429 in the manner set forth above, at least, then because the structure of Kyung ‘456 could increase the reliability of the device.
As incorporated, the DRAM chips (320/330/340) with active faces arranged away from the RDL as taught by Kyung ‘456 would be used as the composition and arrangement of memory die (plurality of 324) of Yu ‘429 so that the plurality of 324 of Yu ‘429 would be DRAM and have active faces arranged facing away from the top of RDL (45).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yu ‘429 in view of Kyung ‘456 in further view of Boo et al. (US 2024/0071980 A1, hereinafter Boo ‘980) in view of the following arguments.
With respect to Claim 6 Yu ‘429 as modified by Kyung ‘456 discloses all limitations of the integrated circuit package of claim 5, and Yu ‘429 as modified by Kyung ‘456 further discloses wherein the dynamic random-access memory dies (320/330/340 as incorporated above) in the stack (stack of 320/330/340 as shown in Fig 15 of Kyung ‘456) are staggered (320/330/340 staggered disclosed in Fig 15 of Kyung ‘456),
But Yu ‘429 as modified by Kyung ‘456 fails to explicitly disclose and wherein the second plurality of interconnects comprises a plurality of wire bonds, each wire bond extending laterally from the stack to the first surface of the redistribution layer.
Nevertheless, in a related endeavor (Fig. 1A-1C of Boo ‘980), Boo ‘980 teaches wherein the second plurality of interconnects (144, Fig 1A of Boo ‘980, Para [0025]) comprises a plurality of wire bonds (a plurality of 144 disclosed in Fig 1A and Para [0025-0026] of Boo ‘980 disclose a plurality of wire bonds 144), each wire bond (144) extending laterally (Fig 1A of Boo ‘980 discloses each 144 extending laterally from the stack) from the stack (140, Fig 1A of Boo ‘980, Para [0025]) to the first surface (top of 116 as shown in Fig 1A of Boo ‘980) of the redistribution layer (116, Fig 1A of Boo ‘980, Para [0021]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Boo ‘980’s teaching of wherein the second plurality of interconnects comprises a plurality of wire bonds, each wire bond extending laterally from the stack to the first surface of the redistribution layer into Yu ‘429 as modified by Kyung ‘456’s device. Yu ‘429 as modified by Kyung ‘456 discloses a semiconductor package comprising a logic die and a memory stack on a redistribution layer wherein the dies are DRAM with active faces away from the redistribution layer. Boo ‘980 discloses a semiconductor package with dies having active faces oriented away from the top of the redistribution layer and each die connected by wire bond to the redistribution layer. The ordinary artisan would have been motivated to modify Yu ‘429 as modified by Kyung ‘456 in the manner set forth above, at least, because, as Boo ‘980 teaches in Para [0026], using a wire bond to directly connect a die to the redistribution layer can “…can provide faster signal travel times and reduce the chance of corrosion (or other physical, electrical, and/or chemical damage) to the signal routing lines” than routing the lines between dies.
As incorporated, the second plurality of interconnects (144) each wire bond extending laterally from the stack to the first surface of the redistribution layer as taught by Boo ‘980 would be used as interconnects of memory die (plurality of 324 of Yu ‘429 as modified by Kyung ‘456 above) such that each 324 of Yu ‘429 as modified by Kyung ‘456 above would be directly connected to the top of RDL 45 by wire bonds 144.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu ‘429 in view of Ahn (US 2023/0060586 A1, hereinafter Ahn ‘586) in view of the following arguments.
With respect to Claim 7 Yu ‘429 discloses all limitations of the integrated circuit package of claim 1, and Yu ‘429 further teaches a memory die (plurality of 324) having an active surface (bottom of 324 with electrical connections 26 as shown in Fig 8 and disclosed in Para [0011]) facing the first surface of the redistribution layer (45).
But Yu ‘429 fails to explicitly disclose wherein each memory die comprises a dynamic random-access memory die.
Nevertheless, in a related endeavor (Fig 1-5 and 8 of Ahn ‘586), Ahn ‘586 teaches wherein each memory die (500/600, Fig 8, Para [0044]) comprises a dynamic random-access memory die (Para [0044] discloses 500/600 as DRAM).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ahn ‘586’s teaching of wherein each memory die comprises a dynamic random-access memory die into Yu ‘429’s device. Yu ‘429 discloses a semiconductor package comprising a logic die and a memory stack on a redistribution layer. Ahn ‘586 teaches a semiconductor package comprising a memory die stack and a logic die and further teaches the memory die as DRAM. The ordinary artisan would have been motivated to modify Lee ‘272 in the manner set forth above, at least, Zhai ‘071 directs the invention of Lee ‘272 to a potential commercial end application.
As incorporated, the teaching of a memory die (500/660) as DRAM of Ahn ‘586 would be used as the memory die (plurality of 324) of Yu ‘429.
With respect to Claim 8 Yu ‘429 as modified by Ahn ‘586 discloses all limitations of the integrated circuit package of claim 7, and Ahn ‘586 further discloses wherein each successive one of the dynamic random-access memory dies (500/600) in the stack (CS of 500/600) is displaced laterally in a first direction (horizontal direction as shown in Fig 8) from a preceding one of the dynamic random-access memory dies in the stack (CS of 500/600)(Fig 8 and Para [0048] disclose that each die is offset horizontally from the die below it), and wherein the second plurality of interconnects (WR3, Fig 8, Para [0052]) comprises a plurality of vertical wire bonds (WR3 disclosed as wire bond in Fig 8 and Para [0052] of Ahn ‘586).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ahn ‘586’s further teaching of wherein each successive one of the dynamic random-access memory dies in the stack is displaced laterally in a first direction from a preceding one of the dynamic random-access memory dies in the stack, and wherein the second plurality of interconnects comprises a plurality of vertical wire bonds into Yu ‘429 as modified by Ahn ‘586’s device. The ordinary artisan would have been motivated to further modify Yu ‘429 as modified by Ahn ‘586 in the manner set forth above, at least, because as Ahn ‘586 teaches the arrangement will save space as Ahn ‘568 teaches in Para [0053] that the arrangement of die to laterally displaced in the horizontal direction allows a direct connection o of the die to the redistribution layer and this arrangement “may result in an advantage in increasing integration of a semiconductor package”.
As incorporated, the teaching of Ahn ‘586 using die (500/600) displaced in a horizontal direction from the preceding one with a vertical wire bond (WR3) connecting bond would be used as the arrangement of die (plurality of 324) of Yu ‘429 second plurality of interconnects (26 on plurality of 324) of Yu ‘429.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yu ‘429 in view of Ahn ‘586 in further view of Heo et al. (US 2020/0020638 A1, hereinafter Heo ‘638) in view of the following arguments.
With respect to Claim 9 Yu ‘429 as modified by Ahn ‘586 discloses all limitations of the integrated circuit package of claim 7, and Ahn ‘586 further discloses wherein each successive one of the dynamic random-access memory dies (500/600) in the stack (CS of 500/600) is displaced laterally in a first direction (horizontal direction as shown in Fig 8) from a preceding one of the dynamic random-access memory dies in the stack (CS of 500/600)(Fig 8 and Para [0048] disclose that each die is offset horizontally from the die below it).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ahn ‘586’s further teaching of wherein each successive one of the dynamic random-access memory dies in the stack is displaced laterally in a first direction from a preceding one of the dynamic random-access memory dies in the stack into Yu ‘429 as modified by Ahn ‘586’s device. The ordinary artisan would have been motivated to further modify Yu ‘429 as modified by Ahn ‘586 in the manner set forth above, at least, because as Ahn ‘586 teaches the arrangement will save space as Ahn ‘568 teaches in Para [0053] that the arrangement of die to laterally displaced in the horizontal direction allows a direct connection o of the die to the redistribution layer and this arrangement “may result in an advantage in increasing integration of a semiconductor package”.
As incorporated, the teaching of Ahn ‘586 using die (500/600) displaced in a horizontal direction from the preceding one would be used as the arrangement of die (plurality of 324) of Yu ‘429.
But Yu ‘429 as modified by Ahn ‘586 fails to explicitly disclose and wherein the second plurality of interconnects comprises a plurality of metal pillars.
Nevertheless, in a related endeavor (Fig 9-11 of Heo ‘638), Heo ‘638 teaches and wherein the second plurality of interconnects (121v/122v/123v/124v, Fig 9 of Heo ‘638, Para [0061]) comprises a plurality of metal pillars (121v/122v/123v/124v as metal pillars disclosed in Fig 9 and Para [0061] of Heo ‘638).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Heo ‘638’s teaching of a wherein the second plurality of interconnects comprises a plurality of interconnects into Yu ‘429 as modified by Ahn ‘586’s device. Yu ‘429 as modified by Ahn ‘586 discloses an integrated circuit package comprising a stack of memory dies on an upper redistribution layer over a logic die on a lower redistribution layer with a plurality of interconnects between the memory stack and upper redistribution layer. Heo ‘638 teaches a memory stack with metal pillar interconnects to an upper redistribution layer over a logic die connected to a lower redistribution layer. The ordinary artisan would have been motivated to modify Yu ‘429 as modified by Ahn ‘586 in the manner set forth above, at least, because Heo ‘638 teaches a well-known method of using metal pillars, or through mold vias, for the well-known advantage of creating electrical connections between a die and a redistribution layer. Therefore it would be obvious to the ordinary artisan make the simple substitution of metal pillars as the second plurality of interconnects. (MPEP 2143 (I)(B)).
As incorporated, the teaching of using metal pillars (121v/122v/123v/124v) of Heo ‘638 would be used as the second plurality of interconnects (26 on plurality of 324) of Yu ‘429 as modified by Ahn ‘586.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘272 in view of Zhai et al. (US 2016/0315071 A1, hereinafter Zhai ‘071) in view of the following arguments.
With respect to Claim 12 Lee ‘272 discloses all limitations of the integrated circuit package of claim 11, but Lee ‘272 fails to explicitly disclose wherein the integrated circuit package is incorporated into a cellular telephone.
Nevertheless, in a related endeavor (Fig 1-10 of Zhai ‘071), Zhai ‘071 teaches wherein the integrated circuit package (integrated circuit package of Fig 10 of Zhai ‘071) is incorporated into a cellular telephone (Para [0005] discloses invention of Zhai ‘071 is directed to a mobile phone. Para [0007] discloses invention of Zhai ‘071 is a semiconductor package comprising DRAM stacked on a logic die).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Zhai ‘071’s teaching of wherein the integrated circuit package is incorporated into a cellular telephone into Lee ‘272’s device. Lee ‘272 discloses a semiconductor package comprising a logic die on a redistribution layer and a memory stack on an upper redistribution layer. Zhai ‘071 also teaches a semiconductor package comprising a logic die on a redistribution layer and a memory stack on an upper redistribution layer and teaches that structure can be used in a mobile phone. The ordinary artisan would have been motivated to modify Lee ‘272 in the manner set forth above, at least, Zhai ‘071 directs the invention of Lee ‘272 to a potential commercial end application.
As incorporated, the teaching of the integrated circuit package of Zhai ‘071 as used in a mobile phone would be used for the application of the integrated circuit package of Lee ‘272.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘272 in view of Kyung ‘456 in view of the following arguments.
With respect to Claim 13 Lee ‘272 discloses all limitations of the integrated circuit package of claim 10, and Lee ‘272 further discloses wherein each memory die having an active surface (top of 220, Fig 7, Para [0066] discloses electrical connections on top of chip 220) facing away (Fig 7 shows top of 220 faces away from top of RDL 210) from the upper surface of the upper redistribution layer (Reference Examiner’s above interpretation of “the upper surface of the upper redistribution layer” as “an upper surface of the upper redistribution layer”) (top of RDL 210 as shown in Fig 7).
But Lee ‘272 fails to explicitly disclose each memory die comprises a dynamic random-access memory die.
Nevertheless, in a related endeavor (Fig 14-15 of Kyung ‘456), Kyung ‘456 teaches wherein each memory die (320/330/340, Fig 15 of Kyung ‘456, Para [0032]) comprises a dynamic random-access memory die (Para [0032] of Kyung ‘456 discloses 320/330/340 as DRAM).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Kyung ‘456’s teaching of wherein each memory die comprises a dynamic random-access memory die into Lee ‘272’s device. Lee ‘272 discloses a semiconductor package comprising a logic die on a redistribution layer and a memory stack on an upper redistribution layer. Kyung ‘456 a teaches a semiconductor package comprising a logic and a stack of memory dies on a redistribution layer. Lee ‘272 discloses in Para [0066] that chip stack 220 are memory chips and in Para [0038] that memory chips can be DRAM, so Lee ‘272 is open to memory chip 220 as a DRAM but it does not explicitly state memory chip 220 is a DRAM. Kyung ‘456 teaches a memory stack of DRAM. The ordinary artisan would have been motivated to modify Lee ‘272 in the manner set forth above, at least because Kyung ‘456 provides end use details to complete the invention of Lee ‘272.
As incorporated, the DRAM chips (320/330/340) as taught by Kyung ‘456 would be used as the memory die (stack of 220) of Lee ‘272.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘272 in view of Kyung ‘456 in further view of Boo ‘980 in view of the following arguments.
With respect to Claim 14 Lee ‘272 as modified by Kyung ‘456 discloses all limitations of the integrated circuit package of claim 13, and Lee ‘272 as modified by Kyung ‘456 further discloses wherein the dynamic random-access memory dies (320/330/340 as incorporated into stack of 220 above) in the at least one stack (stack of 220) are staggered (Fig 7 of Lee ‘272 discloses dies in stack of 220 are staggered),
But Lee ‘272 as modified by Kyung ‘456 fails to explicitly disclose and wherein each wire bond in the plurality of wire bonds extends laterally from the at least one stack to the upper surface of the upper redistribution layer.
Nevertheless, in a related endeavor (Fig. 1A-1C of Boo ‘980), Boo ‘980 teaches wherein each wire bond (144, Fig 1A of Boo ‘980, Para [0025]) in the plurality of wire bonds (a plurality of 144 disclosed in Fig 1A and Para [0025-0026] of Boo ‘980 disclose a plurality of wire bonds 144) extends laterally (Fig 1A of Boo ‘980 discloses each 144 extending laterally from the stack) from the at least one stack (140, Fig 1A of Boo ‘980, Para [0025]) to the upper surface (top of 116 as shown in Fig 1A of Boo ‘980) of the upper redistribution layer (116, Fig 1A of Boo ‘980, Para [0021]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Boo ‘980’s teaching of and wherein each wire bond in the plurality of wire bonds extends laterally from the at least one stack to the upper surface of the upper redistribution layer into Lee ‘272 as modified by Kyung ‘456’s device. Lee ‘272 as modified by Kyung ‘456 discloses a semiconductor package comprising a logic die and a memory stack on a redistribution layer wherein the dies are DRAM with active faces away from the redistribution layer. Boo ‘980 discloses a semiconductor package with dies having active faces oriented away from the top of the redistribution layer and each die connected by wire bond to the redistribution layer. The ordinary artisan would have been motivated to modify Lee ‘272 as modified by Kyung ‘456 in the manner set forth above, at least, because, as Boo ‘980 teaches in Para [0026], using a wire bond to directly connect a die to the redistribution layer can “…can provide faster signal travel times and reduce the chance of corrosion (or other physical, electrical, and/or chemical damage) to the signal routing lines” than routing the lines between dies.
As incorporated, the second plurality of interconnects (144) each wire bond extending laterally from the stack to the upper surface of the redistribution layer as taught by Boo ‘980 would be used as interconnects (WB of Lee ‘272) of memory die (plurality of 220 of Lee ‘272 as modified by Kyung ‘456 above) such that each WB of 220 of Lee ‘272 as modified by Kyung ‘456 above extends laterally from the at least one stack (stack of 220) to the upper surface of the upper redistribution layer (top of RDL 210).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘272 in view of Ahn ‘586 in view of the following arguments.
With respect to Claim 15 Lee ‘272 discloses all limitations of the integrated circuit package of claim 10, but Lee ‘272 fails to explicitly disclose wherein each memory die comprises a dynamic random-access memory die having an active surface facing the upper surface of the upper redistribution layer, and wherein each wire bond in the plurality of wire bonds comprises a vertical wire bond.
Nevertheless, in a related endeavor (Fig 1-5 and 8 of Ahn ‘586), Ahn ‘586 teaches wherein each memory die (500/600, Fig 8, Para [0044]) comprises a dynamic random-access memory die (Para [0044] discloses 500/600 as DRAM) having an active surface (bottom surface of 500/600 as disclosed in Para [0048]) facing the upper surface of the upper redistribution layer (Reference Examiner’s above interpretation of “the upper surface of the upper redistribution layer” as “an upper surface of the upper redistribution layer”) (upper surface of redistribution layer 400)(Fig 8 and Para [0048] disclose active surface of 500/600 facing upper surface of RDL 400) and wherein each wire bond (WR3) in the plurality of wire bonds (plurality of WRS as shown in Fig 8 of Ahn ‘586) comprises a vertical wire bond (WR3 disclosed as wire bond in Fig 8 and Para [0052] of Ahn ‘586).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ahn ‘586’s teaching of wherein each memory die comprises a dynamic random-access memory die having an active surface facing the upper surface of the upper redistribution layer, and wherein each wire bond in the plurality of wire bonds comprises a vertical wire bond into Lee ‘272’s device. Lee ‘272 discloses a semiconductor package comprising a logic die on a redistribution layer and a memory stack on an upper redistribution layer. Ahn ‘586 also teaches a semiconductor package comprising a logic die on a redistribution layer and a memory stack on an upper redistribution layer and further teaches that the memory stack can be formed with the active side of the dies facing the redistribution layer and vertical wire bonds connecting the die to the redistribution layer. The ordinary artisan would have been motivated to modify Lee ‘272 in the manner set forth above, at least, because as Ahn ‘586 teaches in Para [0053] that due to the decrease in the planar area of the package using a die with active face towards the redistribution layer and connected with a vertical wire, this arrangement “may result in an advantage in increasing integration of a semiconductor package”.
As incorporated, the teaching of Ahn ‘586 using die (500/600) having an active surface facing an upper surface of the upper redistribution layer (400) with a vertical wire bond (WR3) connecting bonding would be used as the arrangement of die (stack of 200) and as wire bond (WB) connection to upper redistribution layer (210).
Claims 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn ‘586 in view of Heo ‘638 in view of the following arguments.
With respect to Claim 16 Ahn ‘586 discloses an integrated circuit package (Fig 1-5 and 8), comprising:
an upper redistribution layer (400, Fig 8, Para [0031]);
at least one stack of memory dies (CS of 500/600, Fig 8, Para [0035 and 0044]);
a lower redistribution layer (100, Fig 8, Para [0020]) coupled to (Fig 8 and Para [0067] disclose 100 coupled to 400 through 312) the upper redistribution layer (400) through a plurality of through-mold vias (312, Fig 8, Para [0067]);
a logic die (200, Fig 8, Para [0028] discloses 200 as a logic die); and
a plurality of interconnects (210/220, Fig 8, Para [0029]) coupled between (Para [0029] discloses 210/220 couple to 100) an active surface (bottom surface of 200 as shown in Fig 8 and Para [0028] disclose the active surface of 200 is bottom surface) of the logic die (200) and an upper surface (top of 100) of the lower redistribution layer (100).
But Ahn ‘586 fails to explicitly disclose a first plurality of metal pillars coupled between the at least one stack and the upper redistribution layer.
Nevertheless, in a related endeavor (Fig 9-11 of Heo ‘638), Heo ‘638 teaches a first plurality of metal pillars (121v/122v/123v/124v, Fig 9 of Heo ‘638, Para [0061]) coupled between the at least one stack (stack of 121/122/123/124, Fig 9 of Heo ‘638, Para [0061]) and the upper redistribution layer (142a/142b, Fig 9 of Heo ‘638, Para [0061]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Heo ‘638’s teaching of a first plurality of metal pillars coupled between the at least one stack and the upper redistribution layer into Ahn ‘586’s device. Ahn ‘586 discloses an integrated circuit package comprising a stack of memory dies on an upper redistribution layer over a logic die on a lower redistribution layer with a plurality of interconnects between the memory stack and upper redistribution layer. Heo ‘638 teaches a memory stack with metal pillar interconnects to an upper redistribution layer over a logic die connected to a lower redistribution layer. The ordinary artisan would have been motivated to modify Ahn ‘586 in the manner set forth above, at least, because Heo ‘638 teaches a well-known method of using metal pillars, or through mold vias, for the well-known advantage of creating electrical connections between a die and a redistribution layer.
As incorporated, the teaching of using metal pillars (121v/122v/123v/124v) of Heo ‘638 would be used with the stack of memory dies (CS) of Ahn ‘586 to couple the stack to the upper redistribution layer (100) of Ahn ‘586.
With respect to Claim 18 Ahn ‘586 as modified by Heo ‘638 discloses all limitations of the integrated circuit package of claim 16, and Ahn ‘586 further discloses wherein each memory die (500/600, Fig 8, Para [0044]) comprises a dynamic random-access memory die (Para [0044] discloses 500/600 as DRAM) having an active surface (bottom surface of 500/600 as disclosed in Para [0048]) facing the upper redistribution layer (400)(Fig 8 and Para [0048] disclose active surface of 500/600 facing 400).
With respect to Claim 19 Ahn ‘586 as modified by Heo ‘638 discloses all limitations of the integrated circuit package of claim 18, and Ahn ‘586 further discloses wherein each successive one of the dynamic random-access memory dies (500/600) in the at least one stack (CS of 500/600) is displaced laterally in a first direction (horizontal direction as shown in Fig 8) from a preceding one of the dynamic random-access memory dies in the at least one stack (CS of 500/600)(Fig 8 and Para [0048] disclose that each die is offset horizontally from the die below it).
With respect to Claim 20 Ahn ‘586 as modified by Heo ‘638 discloses all limitations of the integrated circuit package of claim 18, and Heo ‘638 teaches wherein the first plurality of interconnects (121v/122v/123v/124v of Heo ‘638 as incorporated above in Ahn ‘586) comprises a plurality of electroplated metal pillars (121v/122v/123v/124v as metal pillars disclosed in Fig 9 and Para [0061] of Heo ‘638)(Note: the limitation “electroplated” is being treated as a product by process limitation and will not be given patentable weight. (See MPEP 2113(I))).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn ‘586 in view of Heo ‘638 in further view of Yu ‘429 in view of the following arguments.
With respect to Claim 17 Ahn ‘586 as modified by Heo ‘638 discloses all limitations of the integrated circuit package of claim 16, but Ahn ‘586 as modified by Heo ‘638 fails to explicitly disclose wherein the plurality of interconnects comprises a second plurality of metal pillars.
Nevertheless, in a related endeavor (Fig 1-8 of Yu ‘429), Yu ‘429 teaches wherein the plurality of interconnects (26 on die 24, Fig 8 of Yu ‘429, Para [0011]) comprises a second plurality of metal pillars (Para [0011] of Yu ‘429 discloses 26 on 24 as metal pillars).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yu ‘429’s teaching of wherein the plurality of interconnects comprises a second plurality of metal pillars into Ahn ‘586 as modified by Heo ‘638’s device. Ahn ‘586 as modified by Heo ‘638 discloses an integrated circuit package comprising a stack of memory dies on an upper redistribution layer over a logic die on a lower redistribution layer with a plurality of interconnects between the logic die and lower redistribution layer. Yu ‘429 teaches a logic die and memory die stack on a redistribution layer and further teaches the use of metal pillars to connect the logic die to the redistribution layer. The ordinary artisan would have been motivated to modify Ahn ‘586 as modified by Heo ‘638 in the manner set forth above, at least, because as Yu ‘429 teaches in Para [0011] the use of metal pillars on the logic die enables good control of the thickness of the die package leading to a more planar package.
As incorporated, the use of metal pillars (26) as the plurality of interconnects as taught by Yu ‘429 would be used in the plurality of interconnects (210/220) of Ahn ‘586 as modified by Heo ‘638.
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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