DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 6, 17 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. U.S. Patent Publication No. 2013/0093657 (hereinafter Song) in view of Imamura U.S. Patent Publication No. 2004/0108998 (hereinafter Imamura) and further in view of Min et al. U.S. Patent Publication No. 2014/0043306 (hereinafter Min).
Consider claim 1, Song teaches a display apparatus (Figure 2) comprising: a display panel including a first direction data line extending in a first direction (Figure 3, DL2), a plurality of second direction data lines extending in a second direction different from the first direction (Figure 3, DL1), a gate line extending in the second direction (Figure 3, GL) and a pixel connected to the first direction data line and the gate line (Figure 3, 114); a gate driver configured to apply a gate signal to the gate line (Figure 2, 400); and a data driver configured to apply a data voltage to the second direction data lines (Figure 2, 300).
Song does not appear to specifically disclose wherein each of the plurality of second direction data lines has a first end connected to the data driver and an opposite end connected to the first direction data line; configured to apply respective data voltages to the plurality of second direction data lines simultaneously, and wherein the first direction data line connects each of the plurality of second direction data lines without switching.
However, in a related field of endeavor, Imamura teaches an electroluminescent display (abstract) and further teaches wherein each of the plurality of second direction data lines has a first end connected to the data driver and an opposite end connected to the first direction data line (Figures 2, vertical lines from Swa-Swb connected to a single horizontal line); configured to apply respective data voltages to the plurality of second direction data lines simultaneously ([0080], the constant-current output circuit CIm is provided with a pair of D/A converters consisting of a first current output circuit D/Aa and a second current output circuit D/Ab, and is able to selectively supply one of or both a program current and a boost current. [0080], the voltage of the data line), and wherein the first direction data line connects each of the plurality of second direction data lines without switching (Figures 2, vertical lines from Swa-Swb connected directly to a single horizontal line), and wherein each of the plurality of second direction lines is connected to the first direction data line (Figures 2, vertical lines from Swa-Swb connected to a single horizontal line).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide another data supply with the benefit that even in the low-grayscale area in which the program current becomes very small, the voltage of the data line or the gate-source voltage Vgs of the transistor T1 can be rapidly changed to a predetermined value as suggested in [0080].
Song and Imamura do not appear to specifically disclose lines connected in a display area.
However, in a related field of endeavor, Min teaches a display panel (abstract) and further teaches lines connected in a display area (Figure 4, 211-212 and GL1-n).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to connect plurality of second direction lines to first direction line in the display area as taught by Min in order to reduce width of the LCD, provide narrower bezel and/or stronger signal is applied as suggested in [0083] and [0055].
Consider claim 4, Song, Imamura and Min teach all the limitations of claim 1. In addition, Song teaches wherein the display panel comprises: a first first direction data line extending in the first direction (Figure 3, DL2_1); a first second direction data line, a second second direction data line and a third second direction data line which are connected to the first first direction data line (Figure 3, vertical lines connected to horizontal line DL2_1); a second first direction data line extending in the first direction (Figure 3, DL2_2); a fourth second direction data line, a fifth second direction data line and a sixth second direction data line which are connected to the second first direction data line (Figure 3, vertical lines connected to horizontal lines DL2_2); a third first direction data line extending in the first direction (Figure 3, DL2_3); and a seventh second direction data line, an eighth second direction data line and a ninth second direction data line which are connected to the third first direction data line (Figure 3, vertical lines connected to horizontal lines DL2_3), wherein the first direction data line includes the first first direction data line, the second first direction data line and the third first direction data line (vertical lines).
Consider claim 6, Song, Imamura and Min teach all the limitations of claim 1. In addition, Song teaches wherein the display panel comprises: a 1-1 first direction data line extending in the first direction; a first second direction data line which is connected to the 1-1 first direction data line (Figure 3, DL2_1 and DL1_1); a 1-2 first direction data line extending in the first direction and spaced apart from the 1-1 first direction data line (Figure 3, DL2_2); a second second direction data line and a third second direction data line which are connected to the 1-2 first direction data line (Figure 3, vertical lines connected to horizontal line DL2_2); a second first direction data line extending in the first direction (Figure 3, DL2_3); a fourth second direction data line, a fifth second direction data line and a sixth second direction data line which are connected to the second first direction data line (Figure 3, vertical lines connected to horizontal line DL2_3); a third first direction data line extending in the first direction (Figure 3, DL2_4 (dots in figure 3 suggest continuation)); a seventh second direction data line and an eighth second direction data line which are connected to the third first direction data line (vertical lines connected to horizontal line DL2_4); a fourth first direction data line extending in the first direction (Figure 3, DL2_5 (dots in figure 3 suggest continuation)); and a ninth second direction data line which is connected to the fourth first direction data line (vertical line connected to horizontal line DL2_5), wherein the first direction data line includes the 1-1 first direction data line, the 1-2 first direction data line, the second first direction data line, the third first direction data line and the fourth first direction data line (Figure 3, horizontal lines from DL2_1 to DL2_5).
Consider claim 17, it includes the limitations of claim 1 and thus rejected by the same reasoning.
Consider claim 21, it includes the limitations of claim 1 and thus rejected by the same reasoning. In addition, Song teaches an electronic device comprising a display apparatus (Figure 1, 50 and 110).
Claim(s) 2-3, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song, Imamura and Min as applied to claim 1 above, and further in view of Jo et al. U.S. Patent Publication No. 2022/0189408 (hereinafter Jo).
Consider claim 2, Song, Imamura and Min teach all the limitations of claim 1. In addition, Song teaches wherein the display panel comprises a first display area, a second display area disposed adjacent to the first display area in the first direction and a third display area disposed adjacent to the second display area in the first direction (Figure 2 shows at least three display areas adjacent to each other).
Song does not appear to specifically disclose wherein the first display area, the second display area and the third display area are driven with independent frequencies.
However, in a related field of endeavor, Jo teaches display areas in abstract and further teaches wherein the first display area, the second display area and the third display area are driven with independent frequencies ([0095], the first refresh rate to the third refresh rate may be the same or different from each other. Figure 4b, 201, 203 and 401)).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide different refresh rates or frequencies as taught by Jo since each area of a display may be refreshed at a different rate. Thus, allowing a better user experience while reducing power consumption as suggested by Jo in [0028].
Consider claim 3, Song, Imamura, Min and Jo teach all the limitations of claim 2. In addition, Song teaches a gate signal applied to the first display area, a gate signal applied to the second display area and a gate signal applied to the third display area are independently applied (Figure 3, GL1-GL3 are independently applied).
Consider claim 18, it includes the limitations of claim 2 and thus rejected by the same reasoning.
Consider claim 19, it includes the limitations of claim 3 and thus rejected by the same reasoning.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song, Imamura and Min as applied to claim 4 above, and further in view of Kang et al. U.S. Patent Publication No. 2017/0025070 (hereinafter Kang).
Consider claim 5, Song, Imamura and Min teach all the limitations of claim 4. In addition, Song teaches wherein the first first data line includes a first portion and a second portion, and wherein the third first data line includes a third portion (Figure 3, DL2_1 to DL2_3).
Song does not appear to specifically disclose inclined portions.
However, in a related field of endeavor, Kang teaches a display device (abstract) and further teaches inclined portions (Figure 1, D1-D3).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to have inclined portions as taught by Kang with the benefit that the display unit can be formed in various shapes such as a polygonal shape, a circular shape, a shape with several curved and straight line edges, and a certain object shape as suggested in [0092].
Claim(s) 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song, Imamura and Min as applied to claim 1 above, and further in view of Hung et al. U.S. Patent Publication No. 2013/0127801 (hereinafter Hung).
Consider claim 7, Song, Imamura and Min teach all the limitations of claim 1.
Song does not appear to specifically disclose wherein the gate driver extends along a first side of the display panel that extends in the first direction, and wherein the data driver extends along the first side of the display panel.
However, in a related field of endeavor, Hung teaches a display panel (abstract) and further teaches wherein the gate driver extends along a first side of the display panel that extends in the first direction, and wherein the data driver extends along the first side of the display panel (Figure 3, gate driver 356, data driver 352-354).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide gate and data driver along a side as taught by Hung since the circuits can be integrated as suggested in [0025].
Consider claim 8, Song, Imamura, Min and Hung teach all the limitations of claim 7. In addition, Song teaches wherein the data driver includes a plurality of source driving chips connected to the first side of the display panel (Figure 2, 300). In addition, Hung teaches the gate driver is adjacent to a first side of the display panel (Figure 3, gate driver 356, see motivation to combine in claim 6).
Consider claim 9, Song, Imamura and Min teach all the limitations of claim 1. In addition, Song teaches wherein the data driver includes a plurality of source driving chips connected to the display panel (Figure 2, 300).
Song does not appear to specifically disclose the display apparatus further comprises a plurality of source switches disposed between the source driving chips and the second direction data lines.
However, Hung teaches the display apparatus further comprises a plurality of source switches disposed between the source driving chips and the second direction data lines (Figure 3, SW1-SW2, DL1-DL2, 352-354).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide switches with the benefit that the first driving switch SW1 selects the first output ends OUT1 to output the source driving signal according to the first output control signal. In addition, the second data line DL2 is electrically connected to the second output end OUT2 of the second driving switch SW2 for transmitting the source driving signal outputted from the second driving switch SW2 to the pixels P as suggested in [0019].
Consider claim 10, Song, Imamura, Min and Hung teach all the limitations of claim 9.
Song does not appear to specifically disclose wherein the source switches are integrated on the display panel.
However, Hung teaches wherein the source switches are integrated on the display panel (Figure 3, 310-320 and 300).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the claimed invention to have source switches integrated to a display panel in order to form a display panel as suggested in [0019]. In addition, it would have been obvious to integrate for the purpose of design choice as appear to be suggested in [0025].
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song, Imamura, Min and Hung as applied to claim 9 above, and further in view of Lin et al. U.S. Patent Publication No. 2017/0018242 (hereinafter Lin).
Consider claim 11, Song, Imamura, Min and Hung teach all the limitations of claim 9.
Song does not appear to specifically disclose wherein the source switches are integrated in the source driving chip.
However, in a related field of endeavor, Lin teaches a display apparatus (abstract) and further teaches wherein the source switches are integrated in the source driving chip (Figures 8-9, 430, 432_1, 432_2 and 435).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date to provide a source driver with switches as taught by Lin with the benefit that the switch circuit 435 is coupled between the output terminals of the data driving channels 431_1-431_m and the source lines S_1-S_m of the display panel 410 and coupled between the output terminal of the pre-charging voltage generating unit 434 and the source lines S_1-S_m of the display panel 410. In the functional sub-period TF2 of the frame period F2, the switch circuit 435 may select to couple a plurality of corresponding source lines (e.g., some or all of the source lines S_1-S_m) to the output terminal of the pre-charging voltage generating unit 434. Besides, the switch circuit 435 may select to couple the output terminals of the data driving channels 431_1-431_m to the source lines S_1-S_m of the display panel 410 in an one-on-one manner during the scan sub-period TS of the frame period F2 as suggested in [0039].
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song, Imamura and Min as applied to claim 1 above, and further in view of Lin.
Consider claim 12, Song and Imamura teach all the limitations of claim 1.
Song does not appear to specifically disclose wherein the data driver comprises a first source group corresponding to a first display area of the display panel and a second source group corresponding to a second display area of the display panel, wherein the first source group comprises a plurality of first source driving chips, and wherein the second source group comprises a plurality of second source driving chips, the display apparatus further comprising a plurality of first source group switches disposed between the first source driving chips and the second direction data lines in the first display area and a plurality of second source group switches disposed between the second source driving chips and the second direction data lines in the second display area.
However, Lin teaches wherein the data driver comprises a first source group corresponding to a first display area of the display panel (Figure 8, group corresponding to D_1) and a second source group corresponding to a second display area of the display panel (Figure 8, group corresponding to D_2), wherein the first source group comprises a plurality of first source driving chips (433_1 and 431_1), and wherein the second source group comprises a plurality of second source driving chips (433_2 and 431_2), the display apparatus further comprising a plurality of first source group switches disposed between the first source driving chips and the second direction data lines in the first display area (432_1) and a plurality of second source group switches disposed between the second source driving chips and the second direction data lines in the second display area (432_2).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide switches as taught by Lin in order to perform pre-charging and display an image on the display panel as suggested in [0036].
Consider claim 13, Song, Imamura, Min and Lin teach all the limitations of claim 12.
Song does not appear to specifically disclose wherein the first source group switches are turned on and the second source group switches are turned on in a first period, and wherein the first source group switches are turned on and the second source group switches are turned off in a second period.
However, Lin teaches wherein the first source group switches are turned on and the second source group switches are turned on in a first period (Figures 6-8 and [0036], the source driver circuit 430 is able to perform the pre-charging function on all of the pixels of the gate lines in the resultant functional sub-period TF2. Thus, switches 432_1-432_2 are turn on during pre-charging), and wherein the first source group switches are turned on and the second source group switches are turned off in a second period (Figures 6-8 and [0036], After the functional sub-period TF2, in the scan sub-period TS, the source driver circuit 430 correspondingly drives the source lines S_1-S_m of the display panel 410 according to the scan sequence of the gate driver circuit 420, so as to display an image on the display panel 410).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide switches as taught by Lin in order to perform pre-charging and display an image on the display panel as suggested in [0036].
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song, Imamura, Min and Lin as applied to claim 13 above, and further in view of Shin et al. U.S. Patent Publication No. 2021/0358418 (hereinafter Shin).
Consider claim 14, Song, Imamura, Min and Lin teach all the limitations of claim 13. In addition Lin teaches wherein a data voltage is less than a target voltage in the first period (Figures 6-7 and [0036], pre-charging), wherein the data voltage is equal to or greater than the target voltage in the second period (Figures 6-7 and [0036], drives the source lines. The data during this period is greater since it includes a pre-charge voltage) and wherein a first data voltage applied to the first source driving chips and a second data voltage applied to the second source driving chips (Figure 8, D_1-D_2).
Son and Lin do not appear to specifically disclose a first data voltage is the same as a second data voltage applied for the same grayscale value.
However, in a related field of endeavor, Shin teaches a display apparatus (abstract) and further teaches a first data voltage is the same as a second data voltage applied for the same grayscale value (Figures 4-5 and [0105], VD2 and VD4 equal to V1+a).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide same voltage as taught by Shin with the benefit that both of the pixels PX2 and PX4 may be spaced apart from the connection point CP by the same distance (e.g., the first distance d1), and both of the levels of the data voltages VD2 and VD4 applied to the pixels PX2 and PX4 may be equal to each other (e.g., the same as the second level V1+a) as suggested in [0105].
Consider claim 15, Song, Imamura, Min and Lin teach all the limitations of claim 13. In addition Lin teaches wherein the first period is an overdriving period (Figure 7, pre-charging), wherein the second period is a normal driving period (Figure 7, Data in 1st, Data in 2nd row), and wherein a first data voltage applied to the first source driving chips, a second data voltage applied to the second source driving chips (Figure 8, D_1-D_2).
Son and Lin do not appear to specifically disclose wherein a first data voltage is different from a second data voltage for the same grayscale value.
However, Shin teaches wherein a first data voltage is different from a second data voltage for the same grayscale value [0107].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide different voltages for same grayscale as taught by Shin with the benefit when the pixels arranged in the same pixel row display the same grayscale, the plurality of data voltages having the different levels may be output and applied to a plurality of channels, respectively, and the plurality of data voltages may have the levels symmetrical with respect to the connection point CP as suggested in [0107].
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song, Imamura and Min as applied to claim 1 above, and further in view of Wu U.S. Patent Publication No. 2022/0319460 (hereinafter Wu).
Consider claim 16, Song, Imamura and Min teach all the limitations of clam 1.
Song does not appear to specifically disclose wherein the display panel comprises a first pixel and a second pixel which are disposed in a first pixel row and a third pixel and a fourth pixel which are disposed in a second pixel row, wherein the first pixel is connected to a first gate line and a 1-1 first direction data line, wherein the second pixel is connected to the first gate line and a 1-2 first direction data line, wherein the third pixel is connected to the first gate line and a 2-1 first direction data line, wherein the fourth pixel is connected to the first gate line and a 2-2 first direction data line, and wherein the first direction data line includes the 1-1 first direction data line, the 1-2 first direction data line, the 2-1 first direction data line and the 2-2 first direction data line.
However, in a related field of endeavor, Wu teaches an array substrate (abstract) and further teaches wherein the display panel comprises a first pixel and a second pixel which are disposed in a first pixel row and a third pixel and a fourth pixel which are disposed in a second pixel row (Figure 1, pixels corresponding to 111 and pixel corresponding to 112 wherein the first pixel is connected to a first gate line and a 1-1 first direction data line (Figure 1, a first 12a connected to 111 and corresponding data line), wherein the second pixel is connected to the first gate line and a 1-2 first direction data line (Figure 1, a second 12a connected to 111 and corresponding data line), wherein the third pixel is connected to the first gate line and a 2-1 first direction data line (Figure 1, a first 12b connected to 112 and corresponding data line. [0044], a scanning timing of the first scanning line 111 of each row of pixel units may be the same as a scanning timing of the second scanning line 112 of the row of pixel units, thereby shortening the scanning cycle of the scanning lines 11), wherein the fourth pixel is connected to the first gate line and a 2-2 first direction data line (Figure 1, a second 12b connected to 112 and corresponding data line), and wherein the first direction data line includes the 1-1 first direction data line, the 1-2 first direction data line, the 2-1 first direction data line and the 2-2 first direction data line (data lines connected to the pixels).
Therefore, it would have been obvious to one of the ordinary skill art before the effective filing date of the claimed invention to have pixels with the same gate as taught by Song with the benefit that a scanning timing of the first scanning line 111 of each row of pixel units may be the same as a scanning timing of the second scanning line 112 of the row of pixel units, thereby shortening the scanning cycle of the scanning lines 11 and improving the image display effect as suggested in [0044].
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (see new reference Min).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
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