DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the claims filled on 6/14/2024 that has been entered, wherein claims 1-20 are pending.
Election/Restrictions
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-17, drawn to semiconductor device, classified in H10D84/811.
II. Claims 18-20, drawn to a method, classified in H10D 64/01.
The inventions are independent or distinct, each from the other because:
Inventions I and II are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). In the instant case the process of claim 18 can be used to make another and materially different product, than the product of claim 18, wherein the product of claim 1, does not require the stacked nanosheet structure of the process of claim 18.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
Inventions I and II have acquired a separate status in the art as evidenced by their different classification.
Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention.
The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
During a telephone conversation with William Lewis on 6/22/2026 a provisional election was made without traverse to prosecute the invention of the semiconductor device, claims 1-17. Affirmation of this election must be made by applicant in replying to this Office action. Claims 18-20 withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
The examiner has required restriction between product or apparatus claims and process claims. Where applicant elects claims directed to the product/apparatus, and all product/apparatus claims are subsequently found allowable, withdrawn process claims that include all the limitations of the allowable product/apparatus claims should be considered for rejoinder. All claims directed to a nonelected process invention must include all the limitations of an allowable product/apparatus claim for that process invention to be rejoined.
In the event of rejoinder, the requirement for restriction between the product/apparatus claims and the rejoined process claims will be withdrawn, and the rejoined process claims will be fully examined for patentability in accordance with 37 CFR 1.104. Thus, to be allowable, the rejoined claims must meet all criteria for patentability including the requirements of 35 U.S.C. 101, 102, 103 and 112. Until all claims to the elected product/apparatus are found allowable, an otherwise proper restriction requirement between product/apparatus claims and process claims may be maintained. Withdrawn process claims that are not commensurate in scope with an allowable product/apparatus claim will not be rejoined. See MPEP § 821.04. Additionally, in order for rejoinder to occur, applicant is advised that the process claims should be amended during prosecution to require the limitations of the product/apparatus claims. Failure to do so may result in no rejoinder. Further, note that the prohibition against double patenting rejections of 35 U.S.C. 121 does not apply where the restriction requirement is withdrawn by the examiner before the patent issues. See MPEP § 804.01.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 9-13 are rejected under 35 U.S.C. 102(1) as being anticipated by Chou et al. (US 2023/0013764 A1).
Regarding claim 1, Chou teaches a semiconductor device(Fig. 33) comprising:
at least one metal-insulator-metal capacitor device(177, ¶0097), wherein the metal-insulator-metal capacitor device(177, ¶0097) comprises a first electrode(176, ¶0097), an insulator material(174, ¶0097) surrounding the first electrode(176, ¶0097), and a second electrode(172, ¶0097) surrounding the insulator material(174, ¶0097);
at least one transistor device(109, ¶0106) vertically adjacent to the at least one metal-insulator-metal capacitor device(177, ¶0097); and
a first middle-of-line contact(179 connected to 176, ¶0106) connecting the first electrode(176, ¶0097) to a first source/drain region(92, ¶0091) associated with the at least one transistor device(109, ¶0106) and to at least one first frontside interconnect structure(152, ¶0091).
Regarding claim 2, Chou teaches the semiconductor device of claim 1, further comprising:
a second middle-of-line contact(179 connected to 172, ¶0106) connecting the second electrode(172, ¶0097) of the at least one metal-insulator-metal capacitor device(177, ¶0097) to at least one second frontside interconnect structure(156, ¶0090).
Regarding claim 3, Chou teaches the semiconductor device of claim 1, further comprising:
a direct backside source/drain contact(112, ¶0070) connecting at least one second source/drain region(92, ¶0089) associated with the at least one transistor device(109, ¶0106) to one or more backside interconnect structures(122, ¶0092).
Regarding claim 4, Chou teaches the semiconductor device of claim 1, further comprising: a placeholder(96, ¶0086) disposed beneath the first source/drain region(92, ¶0091) associated with the at least one transistor device(109, ¶0106).
Regarding claim 5, Chou teaches the semiconductor device of claim 1, further comprising:
a first dielectric layer(144, ¶0086) disposed between the at least one metal-insulator-metal capacitor device(177, ¶0097) and the at least one transistor device(109, ¶0106), wherein the first dielectric layer(144, ¶0086) electrically isolates the metal-insulator-metal capacitor device(177, ¶0097) from the at least one transistor device(109, ¶0106).
Regarding the limitation of a first “self-aligned” dielectric layer(144, ¶0086), Chou shows all aspects of the semiconductor device according to the instant invention, and that the step of self-aligned, are considered to be process limitations that does not affect the structure of the final device. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. See MPEP 2113.1
Regarding claim 9, Chou teaches the semiconductor device of claim 5, further comprising:
a second dielectric layer(106, ¶0076) disposed below the at least one transistor device(109, ¶0106) that electrically isolates a gate structure(102, ¶0071) associated with the at least one transistor device(109, ¶0106) from a backside interlayer dielectric(124, ¶0076).
Regarding the limitation of a second “self-aligned” dielectric layer(106, ¶0076), Chou shows all aspects of the semiconductor device according to the instant invention, and that the step of self-aligned, are considered to be process limitations that does not affect the structure of the final device. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. See MPEP 2113.1
Regarding claim 10, Chou teaches the semiconductor device of claim 1, further comprising:
at least one deep gate separation region(94, ¶0058) adjacent to the at least one transistor device(109, ¶0106) vertically adjacent to the at least one metal-insulator-metal capacitor device(177, ¶0097).
Regarding claim 11, Chou teaches the semiconductor device of claim 10, wherein the at least one deep gate separation region(170, ¶0095) electrically isolates the first electrode(176, ¶0097) of the at least one metal-insulator-metal capacitor device(177, ¶0097) from at least one adjacent(¶0095) metal-insulator-metal capacitor device(177, ¶0097).
Regarding claim 12, Chou teaches the semiconductor device of claim 10, wherein the at least one deep gate separation region(90, ¶0057) electrically isolates a gate structure(102, ¶0071) of the at least one transistor device(109, ¶0106) from a gate structure(102, ¶0071) of at least one adjacent transistor device(109, ¶0106).
Regarding claim 13, Chou teaches the semiconductor device of claim 1, further comprising: a unit cell(Fig. 33) comprising the at least one metal-insulator-metal capacitor device(177 in right recess, ¶0097), the at least one transistor device(109, ¶0106), and one or more additional metal-insulator-metal capacitor devices(177 in left recess, ¶0097) adjacent to the at least one metal-insulator-metal capacitor device(177 in right recess, ¶0097).
Claims 14-17 are rejected under 35 U.S.C. 102(1) as being anticipated by Lilak et al. (US 2020/0194435 A1).
Regarding claim 14, Lilak teaches a semiconductor device(Fig. 1) comprising:
a transistor device(131, ¶0034) associated with first and second source/drain regions(source/drain region of 161, ¶0038);
a capacitor device(121, ¶0034) vertically adjacent to the transistor device(131, ¶0034), the capacitor device(121, ¶0034) comprising a first electrode(151, 153, ¶0039) an insulator material(156, ¶0039) surrounding the first electrode(151, 153, ¶0039), and a second electrode(154, 142, ¶0039) surrounding the insulator material(156, ¶0039), wherein the first electrode(151, 153, ¶0039) comprises one or more stacked first portions(153, ¶0039) and at least one second portion(151, ¶0039) that is larger(¶0039) than each of the one or more stacked first portions(153, ¶0039); and
a middle-of-line contact(141, ¶0039) connecting the first electrode(151, 153, ¶0039) to the first source/drain region(source region of 161, ¶0038).
Regarding claim 15, Lilak teaches the semiconductor device of claim 14, further comprising:
a direct backside source/drain contact(143, ¶0038) connecting the transistor device(131, ¶0034) to the second source/drain region(drain region of 161, ¶0038).
Regarding claim 16, Lilak teaches the semiconductor device of claim 14, further comprising:
a dielectric layer(111, ¶0037) disposed between the capacitor device(121, ¶0034) and the transistor device(131, ¶0034);
a shallow gate separation region(167, ¶0038) separating the first electrode(151, 153, ¶0039) and the second electrode(154, 142, ¶0039) from a gate structure(162, ¶0038) of the transistor device(131, ¶0034); and
a spacer(113, ¶0035) separating the second electrode(154, 142, ¶0039) from the gate structure(162, ¶0038) of the transistor device(131, ¶0034).
Regarding the limitation of a “self-aligned” dielectric layer(111, ¶0037), Lilak shows all aspects of the semiconductor device according to the instant invention, and that the step of self-aligned, are considered to be process limitations that does not affect the structure of the final device. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. See MPEP 2113.1
Regarding claim 17, Lilak teaches the semiconductor device of claim 14, further comprising:
at least one deep gate separation region(113, ¶0035) adjacent to the transistor device(131, ¶0034), wherein the at least one deep gate separation region(113, ¶0035) separates at least one of:
the first electrode(151, 153, ¶0039) from at least one electrode of an adjacent capacitor device(121, ¶0034); and
a gate structure(162, ¶0038) of the transistor device(131, ¶0034) from a gate structure(162, ¶0038) of at least one adjacent transistor device(131, ¶0034).
Allowable Subject Matter
Claims 6-8 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, Chou teaches the semiconductor device of claim 5 but does not teach a shallow gate separation region that electrically isolates the first electrode(176, ¶0097) and the second electrode(172, ¶0097) from a gate structure of the at least one transistor device(109, ¶0106), wherein the shallow gate separation region contacts vertical sides of at least two stacked horizontal portions of the first electrode(176, ¶0097) and a first vertical side of the first self-aligned dielectric layer(144, ¶0086).
Regarding dependent claim 6, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “a shallow gate separation region that electrically isolates the first electrode and the second electrode from a gate structure of the at least one transistor device, wherein the shallow gate separation region contacts vertical sides of at least two stacked horizontal portions of the first electrode and a first vertical side of the first self-aligned dielectric layer”.
Claims 7 and 8 depend on claim 6 and inherit the allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAURA M DYKES/Examiner, Art Unit 2892
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