DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-8, and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang (US 2023/0335610).
With regard to claim 1, figs. 4 and 11B of Huang discloses an integrated circuit device 100 comprising: a substrate 102; a fin-type active region 106 that extends in a first horizontal direction Y on the substrate 102; a gate line 168 on the fin-type active region 168, wherein the gate line 168 extends in a second horizontal direction X that intersects the first horizontal direction Y; and a gate dielectric film 166 that is in contact with a lower surface and opposite sidewalls of the gate line 168, wherein a gate upper surface of the gate line 168 includes a portion that has a decreasing distance from the substrate 102 in a vertical direction Z as a distance between the portion of the gate upper surface of the gate line 168 and the gate dielectric film 166 in the first horizontal direction Y decreases.
With regard to claim 2, fig. 11B of Huang discloses a capping insulating pattern 141 that has a capping lower surface (bottom of 141) that is in contact with the gate upper surface of the gate line 168 and an upper surface of the gate dielectric film 166, wherein the capping lower surface (bottom of 141) of the capping insulating pattern 141 includes a portion that has a decreasing distance from the substrate 102 in the vertical direction Z as a distance between the capping lower surface (bottom of 141) of the capping insulating pattern 141 and the gate dielectric film 166 in the first horizontal direction Y decreases.
With regard to claim 3, fig. 11B of Huang discloses a pair of insulating spacers 140 respectively on the opposite sidewalls of the gate line 168; and a capping insulating pattern 141 that has a capping lower surface (bottom of 141) that is in contact with the gate upper surface (top of 168) of the gate line 168, an upper surface of the gate dielectric film 166, and upper surfaces of the pair of insulating spacers 140, wherein the capping lower surface (bottom of 141) of the capping insulating pattern 141 includes a portion that has a decreasing distance from the substrate 102 in the vertical direction as a distance between the capping lower surface (bottom of 141) of the capping insulating pattern 141 and each of the pair of insulating spacers 140 in the first horizontal direction Y decreases.
With regard to claim 4, fig. 11B of Huang disclose a capping insulating pattern 141 that has a capping lower surface (bottom of 141) that is in contact with the gate upper surface of the gate line 168 and an upper surface of the gate dielectric film 166, wherein the capping insulating pattern 141 comprises: a center insulating portion (center of 141) that overlaps the gate line 168 in the vertical direction Z; and a pair of side insulating portions (sides of 141) that are integrally connected with the center insulating portion (center of 141)and each face the gate line 168 at a distance that is closer than the gate upper surface (top of 168) of the gate line 168 to the substrate 102.
With regard to claim 5, fig. 11B of Huang discloses respective lowermost portions of the pair of side insulating portions (sides of 141) are equidistant from the substrate 102, and the pair of side insulating portions (sides of 141) are symmetrical with each other about the gate line 141.
With regard to claim 7, figs. 11B and 15A-15B of Huang a capping insulating pattern 141 that is in contact with the gate upper surface (top of 168) of the gate line 168 and an upper surface of the gate dielectric film 166; a source/drain region 152 on the fin-type active region 106, wherein the source/drain region 152 is adjacent to the gate line 168 in the first horizontal direction Y; an insulating structure 160 on the source/drain region 152; and a source/drain contact 172 that extends in the insulating structure 160 in the vertical direction Z to be electrically connected to the source/drain region 152, wherein a portion of the gate line 168 faces the source/drain contact 152 in the first horizontal direction Y, and wherein the capping insulating pattern 141 includes a portion between the gate line 168 and the source/drain contact 172 in the first horizontal direction Y.
With regard to claim 8, figs. 11B and 15A-15B of Huang discloses a gate contact 189 that is on and electrically connected to the gate line 168, wherein the gate line 168 has a portion that is convex toward the gate contact 189.
With regard to claim 19, figs. 4, 11B, and 15A-15B of Huang discloses an integrated circuit device 100 comprising: a substrate 102; a fin-type active region 102P that extends in a first horizontal direction Y on the substrate 102; a nanosheet stack (“nanosheet channel FETs”, par [0018]) on a fin upper surface 106 of the fin-type active region 106, wherein the nanosheet stack (“nanosheet channel FETs”, par [0018]) is spaced apart from the fin upper surface 106 in a vertical direction Z, and wherein the nanosheet stack (“nanosheet channel FETs”, par [0018]) includes at least one nanosheet (“nanosheet channel FETs”, par [0018]); a gate line 168 on the fin-type active region 102P, wherein the gate line 168 extends around the at least one nanosheet (“Horizontal Gate All Around (HGAA) FETs”, par [0018]), wherein the gate line 168 extends in a second horizontal direction X; a gate dielectric film 166 that is in contact with a lower surface and opposite sidewalls of the gate line 168; a pair of insulating spacers 141 on the opposite sidewalls of the gate line 168, wherein the pair of insulating spacers 141 are each spaced apart from the gate line 168 in the first horizontal direction Y with the gate dielectric film 166 therebetween; and a capping insulating pattern 141 that includes a capping lower surface (bottom of 141), wherein the capping lower surface (bottom of 141) is in contact with a gate upper surface of the gate line 168, an upper surface (top of 166) of the gate dielectric film 166, and upper surfaces (upper side surfaces of 141) of the pair of insulating spacers 141, wherein the gate upper surface (top of 168) of the gate line 168 includes a portion that has a decreasing distance from the substrate 102 in the vertical direction Z as a distance between the portion of the gate upper surface of the gate line 168 and each of the pair of insulating spacers 140 in the first horizontal direction Y decreases, and wherein the capping insulating pattern 141 includes a center insulating portion (center of 141) that overlaps the gate line 168 in the vertical direction Z and a pair of side insulating portions (sides of 141) that are integrally connected with the center insulating portion (center of 141) and each face the gate line 168 at a distance that is closer than the gate upper surface (top of 168) of the gate line 168 to the substrate 102.
With regard to claim 20, figs. 4, 11B, and 15A-15B of Huang discloses a source/drain region 152 on the fin-type active region 106, wherein the source/drain region 152 is adjacent to the gate line 168 in the first horizontal direction Y; and a source/drain contact 172 on the source/drain region 152, wherein the source/drain contact 172 is electrically connected to the source/drain region 152, wherein the source/drain contact 172 faces the gate line 168 in the first horizontal direction Y, and wherein the capping insulating pattern 141 includes a portion (side portions of 141) between the gate line 168 and the source/drain contact 172 in the first horizontal direction Y.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-11, 13-14, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2023/0335610) in view of Huang (US 12,336,215) (“Huang 2”).
With regard to claim 10, figs. 4 and 11A-11B of Huang discloses an integrated circuit device comprising: a substrate 102 that includes a first device area 102P and a second device area 102N; a first fin-type active region 106 on the substrate 102 in the first device area 102P, wherein the first fin-type active region 106 extends in a first horizontal direction Y; a first gate line 168 on the first fin-type active region 102P, wherein the first gate line 168 extends in a second horizontal direction X that intersects the first horizontal direction Y, and wherein the first gate line 168 has a first width (width of 168 in Y direction) in the first horizontal direction Y; a first gate dielectric film 166 that is in contact with a lower surface (bottom of 168) and opposite sidewalls (side of 168) of the first gate line 166; a second fin-type active region 102N on the substrate 102 in the second device area 102N, wherein the second fin-type active region 10N extends in the first horizontal direction Y; a second gate line (168 in 102N) on the second fin-type active region (102N), wherein the second gate line (168 of 102N) extends in the second horizontal direction X, and a second gate dielectric film (166 in 102N) that is in contact with a lower surface and opposite sidewalls of the second gate line (168 in 102N), wherein a first gate upper surface of the first gate line (168 in 102P) includes a portion that has a decreasing distance from the substrate in a vertical direction Z as a distance between the portion of the first gate upper surface (top of 168 in 102P) of the first gate line (168 in 102P) and the first gate dielectric film (166 in 102P) in the first horizontal direction Y decreases, and wherein a second gate upper surface (top of 168 in 102N) of the second gate line (168 in 102N) includes a portion that has a decreasing distance from the substrate 102 in the vertical direction Z as a distance between the portion of the second gate upper surface of the second gate line (168 in 102N) and the second gate dielectric film (166 in 102N) in the first horizontal direction Y decreases.
Huang does not disclose that the second gate line has a second width that is greater in the first horizontal direction than the first width of the first gate line.
However, fig. 3 of Huang 2 discloses that the second gate line 140 has a second width that is greater in the first horizontal direction (left to right in fig. 3) than the first width of the first gate line 140b.
Therefore, it would have been obvious to one of ordinary skill in the art to form the gates of Huang with the different widths as taught Huang 2 in order to provide different properties such as faster switching speeds or lower leakage current. See col. 7 ll. 61-63 of Huang 2.
With regard to claim 11, figs. 4 and 11A-11B of Huang discloses an uppermost portion of the second gate upper surface (top of 168 in 102N) is at a center point of the second gate upper surface (top of 168 in 102N) in the first horizontal direction Y.
With regard to claim 13, figs. 4 and 11A-11B of Huang discloses a pair of first insulating spacers (140 in 102P) on the opposite sidewalls of the first gate line (168 in 102P); a first capping insulating pattern (141 in 102P) that has a first capping lower surface (bottom of 141 in 102P) that is in contact with the first gate upper surface of the first gate line (168 in 102P), an upper surface of the first gate dielectric film (166 in 102P), and upper surfaces (top side surface of 140 in 102P) of the pair of first insulating spacers (140 in 102P); a pair of second insulating spacers (140 in 102N) on the opposite sidewalls of the second gate line (168 in 102N); and a second capping insulating pattern (141 in 102N) that has a second capping lower surface (bottom of 141 in 102N) that is in contact with the second gate upper surface (top of 168 in 102N) of the second gate line (168 in 102N), an upper surface of the second gate dielectric film (166 in 102N), and upper surfaces (upper sidewall of 140 in 102N) of the pair of second insulating spacers (140 in 102N), wherein the first capping lower surface (bottom of 141 in 102P) of the first capping insulating pattern (141 in 102P) includes a portion that has a decreasing distance from the substrate 102 in the vertical direction as a distance between the portion of the first capping lower surface (bottom of 141 in 102P) of the first capping insulating pattern (141 in 102P) and each of the pair of first insulating spacers (140 in 102P) in the first horizontal direction Y decreases, and wherein the second capping lower surface (bottom of 141 in 102N) of the second capping insulating pattern (141 in 102N) includes a portion that has a decreasing distance from the substrate 102 in the vertical direction Z as a distance between the portion of the second capping lower (141 in 102N) surface of the second capping insulating pattern (141 in 102N) and each of the pair of second insulating spacers (140 in 102N) in the first horizontal direction Y decreases.
With regard to claim 14, figs. 4 and 11A-11B of Huang discloses that the first capping insulating pattern (141 in 102P) comprises: a first center insulating portion (center of 141) that overlaps the first gate line (168 in 102P) in the vertical direction Z; and a pair of first side insulating portions (sides of 141 in 102P) that are integrally connected with the first center insulating portion (center of 141) and each face the first gate line (168 in 102P) at a distance that is closer than the first gate upper surface of the first gate line (168 in 102P) to the substrate 102, the second capping insulating pattern (141 in 102N) comprises: a second center insulating portion (center of 141 in 102N) that overlaps the second gate line (158 in 102N) in the vertical direction Z; and a pair of second side insulating portions (sides of 141 in 102N) that are integrally connected with the second center insulating portion (center of 141 in 102N) and each face the second gate line (168 in 102N) at a distance that is closer than the second gate upper surface of the second gate line (168 in 102N) to the substrate 102, wherein the pair of first side insulating portions (sides of 141 in 102P) are symmetrical with each other about the first gate line (168 in 102P), and wherein the pair of second side insulating portions (sides of 141 in 102N) are symmetrical with each other about the second gate line (168 in 102N).
With regard to claim 17, figs. 4, 11A-11B, and 14A of Huang discloses a first capping insulating pattern (141 in 102P) on the first gate upper surface of the first gate line (168 in 102P); a first source/drain region (152 in 102P) on the first fin-type active region (106 in 102P), wherein the first source/drain region 152 is adjacent to the first gate line 168 in the first horizontal direction Y; and a first source/drain contact 172 on the first source/drain region 152, wherein the first source/drain contact 172 is electrically connected to the first source/drain region 152, wherein the first capping insulating pattern 141 includes a portion between the first gate line 168 and the first source/drain contact 172 in the first horizontal direction Y.
With regard to claim 18, figs. 4 and 11A-11B of Huang discloses a second capping insulating pattern (141 in 102N) on the second gate upper surface of the second gate line (168 in 102N); a second source/drain region (152 in 102N) on the second fin-type active region (106 in 102N), wherein the second source/drain region (152 in 102N) is adjacent to the second gate line (168 in 102N) in the first horizontal direction Y; and a second source/drain contact (172 in 102N) on the second source/drain region (152 in 102N), wherein the second source/drain contact (172 in 102N) is electrically connected to the second source/drain region (152 in 102N), wherein the second capping insulating pattern (141 in 102N) includes a portion between the second gate line (168 in 102N) and the second source/drain contact (172 in 102N) in the first horizontal direction Y.
Allowable Subject Matter
Claims 6, 9, 12, and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With regard to claim 6, fig. 11B of Huang (US 2023/0335610) disclose that the respective lowermost portions of the pair of side insulating portions (side of 141) are at the same distance to the substrate but not that they are at different distances from the substrate.
With regard to claim 9, figs. 11B of Huang discloses a capping insulating pattern 141 that has a capping lower surface (bottom of 141) and a capping upper surface (top of 141), wherein the capping lower surface (bottom of 141) and the capping upper surface (top of 141) are opposite to each other in the vertical direction Z, wherein the capping lower surface (bottom of 141) is in contact with the gate upper surface (top of 168) of the gate line 168 and an upper surface of the gate dielectric film 166. However, Huang does not disclose that the capping insulating pattern 141 includes a protrusion that is adjacent to the capping upper surface (top of 141) and protrude outwards in the first horizontal direction Y.
With regard to claim 12, figs. 11B of Huang discloses an uppermost portion of the second gate upper surface (168 in 102N) at a center position but not at a position biased to one side in the first horizontal direction from a center point of the second gate upper surface in the first horizontal direction.
With regard to claim 15, fig. 11B of Huang discloses the pair of first side insulating portions (sides of 141 in 102P) are symmetrical but do not disclose the pair of first side insulating portions are asymmetrical with each other.
With regard to claim 16, fig. 11B of Huang discloses the first and second capping insulating pattern 141 but does not disclose at least one of the first capping insulating pattern and the second capping insulating pattern has an upper portion that protrudes outwards in the first horizontal direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at 571 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
Prosecution Insights