DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on July 22, 2026.
Claims 1-20 are pending. Claims 1, 3, 9, 11-12, 15 and 17 are amended. Claims 1, 9 and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 and 15 are objected to because of the following informalities:
In Claim 1, line 9, “the data of the memory cells” should be --the raw data of the memory cells--.
In Claim 15, line 4, “the circuitry being configured to;” should be --the circuitry being configured to:--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 15-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kawase et al. (US 20140063955) in view of Radke (US 20080072120).
Regarding independent claim 1, Kawase et al. disclose a method of operating a memory device, comprising the steps of:
preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the memory cells containing data [see Fig. 4 with respect to Fig. 3, para. 46-48];
receiving from a host an instruction to read the data of a selected word line of the plurality of word lines [see Fig. 1, the NAND flash memory 21 receiving a write command, a read command, and an erase command from the host device 10, para. 34. The controller 22 sends a read command and a page address to the NAND flash memory 21, which reads data from the memory cell array 31, para. 68];
performing a sensing operation on the selected word line to read raw data of the selected word line [this embodiment is configured to read data by setting, as reference voltages, the upper limit voltage and lower limit voltage between the threshold voltage distribution corresponding to the Er level and the threshold voltage distribution corresponding to the A level, para 61. The controller 22 reads data from the NAND flash memory 21, para. 69];
determining if the data of the memory cells of the selected word line includes any errors [Fig. 9, steps S103-S104, the controller counts, from this read data, the number of error cells having threshold voltages between the two threshold voltage distributions in step S103 and determines whether the number of error cells counted is less than or equal to the error specified value set in step S100 (step S104), para. 61 as well as para. 72-74];
in response to a determination that the raw data of the memory cells of the selected word line contains any errors, sending the raw data of the selected word line to an error correction code engine, and performing an error correction operation on the raw data and sending corrected data to the host via a host interface [Fig. 9: steps S106-S108, upon determining in step S104 that the number of error cells exceeds the error specified value, the controller 22 reads page data from the NAND flash memory 21 and stores the read page data in the data buffer 27 (step S106). The page data read at the step S106 corresponds to the same page as that indicated by the intra-page addresses set in step S100 and are the entire data of the page instead of partial data corresponding to the intra-page addresses. The ECC circuit 28 then performs error correction of the page data on an ECC frame basis by using the error correction codes contained in the ECC frames (step S107). The ECC circuit 28 stores the corrected page data in the data buffer 27 upon removing the error correction codes, para. 76. The data buffer 27 temporarily stores a predetermined amount of data when transmitting data read from the NAND flash memory 21 to the host device 10, para. 35]; and
in response to a determination that the raw data of the memory cells of the selected word line does not include any errors, bypassing the error correction code engine, skipping the error correction operation [in this direct copy processing, since no error correction is performed, the control circuit 38 does not transfer the page data to the controller 22. That is, the ECC circuit 28 has nothing to do with direct copy processing, para. 75].
However, Kawase et al. are silent with respect to sending the raw data as uncorrected data to the host via host interface.
Radke teaches in response to a determination that the raw data of the memory cells of the selected word line contains any errors, sending the raw data of the selected word line to an error correction code engine, and performing an error correction operation on the raw data and sending corrected data to the host via a host interface [see Fig. 4, if the data block is corrupted, the Reed-Solomon ECC checker/syndrome generator hardware 408 signals 412 a (typically internal) microprocessor or dedicated ECC correction hardware 416 to correct the errors by utilizing a Reed-Solomon ECC correction algorithm. After applying the correction to the data buffer 406, the microprocessor 416 signals 420 the host transfer hardware 414 to begin transferring the data block from the data buffer 406 out through the host interface 404, para. 39]; and in response to a determination that the raw data of the memory cells of the selected word line does not include any errors, bypassing the error correction code engine, skipping the error correction operation and sending the raw data as uncorrected data to the host via the host interface [see Fig. 4, once the data block is read and evaluated, the Reed-Solomon ECC checker/syndrome generator hardware 408 signals 410 through the host transfer hardware 414 to a host interface 404 to start the data transfer if the data block is correct without running the ECC correction hardware 416, para. 39].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Radke to the teaching of Kawase et al. such that applying Radke’s conditional host transfer technique to the NAND read system of Kawase et al. to avoid unnecessary error correction latency while still correcting error data, thereby predictably improving read performance while maintaining data reliability.
Regarding claim 2, Kawase et al. in combination with Radke teach the limitations with respect to claim 1.
Furthermore, Kawase et al. disclose wherein the step of performing the sensing operation on the selected word line includes comparing threshold voltages of the memory cells of the selected word line to two different reference voltages [Fig. 9, steps S101-S103, the controller counts, from this read data in step S101 and S102, the number of error cells having threshold voltages between the two threshold voltage distributions in step S103, para. 61 as well as para. 72-74].
Regarding claim 3, Kawase et al. in combination with Radke teach the limitations with respect to claim 2.
Furthermore, Kawase et al. disclose wherein the step of determining if the data of the selected word line contains any errors includes the step of determining if any of the memory cells of the selected word line have threshold voltages between the two different reference voltages [Fig. 9: step 103-104, the controller counts, from this read data in step S101 and S102, the number of error cells having threshold voltages between the two threshold voltage distributions in step S103 and determines whether the number of error cells counted in step S103 is less than or equal to the error specified value set in step S100 (step S104), para. 61 as well as para. 72-74].
Regarding claim 5, Kawase et al. in combination with Radke teach the limitations with respect to claim 3.
Furthermore, Kawase et al. disclose wherein the data is in a single bit per memory cell (SLC) storage format [para. 63 as well as para. 86] and wherein the two reference voltages include a first SLC reference voltage and a second SLC reference voltage [Fig. 9: step S101-S102, reads data from the NAND flash memory 21 by using the upper limit voltage and the lower limit voltage, para. 68-69].
Regarding independent claim 15, Kawase et al. disclose a memory device [Fig. 1: 20, para. 29-31], comprising:
a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the memory cells containing data [see Fig. 4 with respect to Fig. 3, para. 46-48]; and
circuitry [Fig. 1: 22] for reading the data in the memory cells [para. 68], the circuity including an error correction engine [Fig. 1: 28] and a host interface [Fig. 1: 23, para. 31] and being configured to:
receive from a host an instruction to read the data of a selected word line of the plurality of word lines [see Fig. 1, the NAND flash memory 21 receiving a write command, a read command, and an erase command from the host device 10, para. 34. The controller 22 sends a read command and a page address to the NAND flash memory 21, which reads data from the memory cell array 31, para. 68];
perform a sensing operation on the selected word line to read raw data of the selected word line [this embodiment is configured to read data by setting, as reference voltages, the upper limit voltage and lower limit voltage between the threshold voltage distribution corresponding to the Er level and the threshold voltage distribution corresponding to the A level, para 61. The controller 22 reads data from the NAND flash memory 21, para. 69];
determine if the raw data of the memory cells of the selected word line includes any errors [Fig. 9, steps S103-S104, the controller counts, from this read data, the number of error cells having threshold voltages between the two threshold voltage distributions in step S103 and determines whether the number of error cells counted is less than or equal to the error specified value set in step S100 (step S104), para. 61 as well as para. 72-74];
in response to a determination that the raw data of the memory cells of the selected word line contains any errors, send the raw data of the selected word line to the error correction engine and perform an error correction operation on the raw data and sending corrected data to the host via the host interface [Fig. 9: steps S106-S108, upon determining in step S104 that the number of error cells exceeds the error specified value, the controller 22 reads page data from the NAND flash memory 21 and stores the read page data in the data buffer 27 (step S106). The page data read at the step S106 corresponds to the same page as that indicated by the intra-page addresses set in step S100 and are the entire data of the page instead of partial data corresponding to the intra-page addresses. The ECC circuit 28 then performs error correction of the page data on an ECC frame basis by using the error correction codes contained in the ECC frames (step S107). The ECC circuit 28 stores the corrected page data in the data buffer 27 upon removing the error correction codes, para. 76. The data buffer 27 temporarily stores a predetermined amount of data when transmitting data read from the NAND flash memory 21 to the host device 10, para. 35]; and
in response to a determination that the raw data of the memory cells of the selected word line does not include any errors, bypass the error correction code engine, skip the error correction operation [in this direct copy processing, since no error correction is performed, the control circuit 38 does not transfer the page data to the controller 22. That is, the ECC circuit 28 has nothing to do with direct copy processing, para. 75].
However, Kawase et al. are silent with respect to sending the raw data as uncorrected data to the host via host interface.
Radke teaches in response to a determination that the raw data of the memory cells of the selected word line contains any errors, sending the raw data of the selected word line to an error correction code engine, and performing an error correction operation on the raw data and sending corrected data to the host via a host interface [see Fig. 4, if the data block is corrupted, the Reed-Solomon ECC checker/syndrome generator hardware 408 signals 412 a (typically internal) microprocessor or dedicated ECC correction hardware 416 to correct the errors by utilizing a Reed-Solomon ECC correction algorithm. After applying the correction to the data buffer 406, the microprocessor 416 signals 420 the host transfer hardware 414 to begin transferring the data block from the data buffer 406 out through the host interface 404, para. 39]; and in response to a determination that the raw data of the memory cells of the selected word line does not include any errors, bypassing the error correction code engine, skipping the error correction operation and sending the raw data as uncorrected data to the host via the host interface [see Fig. 4, once the data block is read and evaluated, the Reed-Solomon ECC checker/syndrome generator hardware 408 signals 410 through the host transfer hardware 414 to a host interface 404 to start the data transfer if the data block is correct without running the ECC correction hardware 416, para. 39].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Radke to the teaching of Kawase et al. such that applying Radke’s conditional host transfer technique to the NAND read system of Kawase et al. to avoid unnecessary error correction latency while still correcting error data, thereby predictably improving read performance while maintaining data reliability.
Regarding claim 16, Kawase et al. in combination with Radke teach the limitations with respect to claim 15.
Furthermore, Kawase et al. disclose wherein when performing the sensing operation on the selected word line, the circuitry compares threshold voltages of the memory cells of the selected word line to two different reference voltages [Fig. 9, steps S101-S103, the controller counts, from this read data in step S101 and S102, the number of error cells having threshold voltages between the two threshold voltage distributions in step S103, para. 61 as well as para. 72-74].
Regarding claim 17, Kawase et al. in combination with Radke teach the limitations with respect to claim 16.
Furthermore, Kawase et al. disclose wherein when determining if the data of the selected word line contains any errors, the circuitry determes if any of the memory cells of the selected word line have threshold voltages between the two different reference voltages [Fig. 9: step 103-104, the controller counts, from this read data in step S101 and S102, the number of error cells having threshold voltages between the two threshold voltage distributions in step S103 and determines whether the number of error cells counted in step S103 is less than or equal to the error specified value set in step S100 (step S104), para. 61 as well as para. 72-74].
Regarding claim 19, Kawase et al. in combination with Radke teach the limitations with respect to claim 17.
Furthermore, Kawase et al. disclose wherein the data is in a single bit per memory cell (SLC) storage format [para. 63 as well as para. 86] and wherein the two reference voltages include a first SLC reference voltage and a second SLC reference voltage [Fig. 9: step S101-S102, reads data from the NAND flash memory 21 by using the upper limit voltage and the lower limit voltage, para. 68-69].
Claims 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kawase et al. (US 20140063955) in view of Radke (US 20080072120) as applied to claims 1 and 15 above, and further in view of Louie et al. (US 9472298).
Regarding claim 4, Kawase et al. in combination with Radke teach the limitations with respect to claim 3.
However, Kawase et al. in combination with Radke are silent with respect to wherein the sensing operation includes the steps of discharging a sense node through a selected NAND string while a first reference voltage is applied to the selected word line and then discharging the sense node through the selected NAND string while a second reference voltage is applied to the selected word line.
Louie et al. teach wherein the sensing operation includes the steps of discharging a sense node through a selected NAND string while a first reference voltage is applied to the selected word line [see Fig. 11, between t4 and t5, the sense node SEN discharges while voltage level V1 is applied to word line, col. 21, lines 59-62 as well as col. 22, lines 22-28] and then discharging the sense node through the selected NAND string while a second reference voltage is applied to the selected word line [[see Fig. 11, the voltage level on the word line is changed (e.g., ramped up) to voltage V2 after time t5 and after that the sense node SEN discharges (two different discharge rates are depicted), col. 22, lines 27-28 as well as col. 23, lines 1-4].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Louie et al. to the teaching of Kawase et al. in combination with Radke such that incorporating the step of discharging sense node through a selected NAND string while a reference voltage is applied to the selected word line as taught by Louie et al. into sense operation of Kawase et al. in combination with Radke to reduce read latency while yielding predictable two-reference sensing results.
Regarding claim 18, Kawase et al. in combination with Radke teach the limitations with respect to claim 17.
However, Kawase et al. in combination with Radke are silent with respect to wherein when performing the sensing operation, the circuitry discharges a sense node through a selected NAND string while a first reference voltage is applied to the selected word line and then discharging the sense node through the selected NAND string while a second reference voltage is applied to the selected word line.
Louie et al. teach wherein the sensing operation includes the steps of discharging a sense node through a selected NAND string while a first reference voltage is applied to the selected word line [see Fig. 11, between t4 and t5, the sense node SEN discharges while voltage level V1 is applied to word line, col. 21, lines 59-62 as well as col. 22, lines 22-28] and then discharging the sense node through the selected NAND string while a second reference voltage is applied to the selected word line [[see Fig. 11, the voltage level on the word line is changed (e.g., ramped up) to voltage V2 after time t5 and after that the sense node SEN discharges (two different discharge rates are depicted), col. 22, lines 27-28 as well as col. 23, lines 1-4].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Louie et al. to the teaching of Kawase et al. in combination with Radke such that incorporating the step of discharging sense node through a selected NAND string while a reference voltage is applied to the selected word line as taught by Louie et al. into sense operation of Kawase et al. in combination with Radke to reduce read latency while yielding predictable two-reference sensing results.
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kawase et al. (US 20140063955) in view of Radke (US 20080072120) as applied to claims 5 and 17 above, and further in view of Tseng et al. (US 20180374518).
Regarding claim 6, Kawase et al. in combination with Radke teach the limitations with respect to claim 5.
However, Kawase et al. in combination with Radke are silent with respect to only a single discharge of a sense node for each of the memory cells.
Tseng et al. teach a single discharge of a sense node for each of the memory cells [Fig. 6B: step 624, connecting the sense node to the bit line to allow the sense node voltage to discharge into the bit line, para. 109] that is different from the step of performing the sensing operation and comparing the threshold voltages of the memory cells of the selected word line to two reference voltages as taught by Kawase et al.
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Tseng et al. to the teaching of Kawase et al. in combination with Radke such that modifying sensing operation of Kawase et al. in combination with Radke to obtain the comparison between the threshold voltages of the memory cells of the selected word line and two reference voltages using Tseng et al.’s single discharge technique to improve speed and efficiency without changing fundamental operation of Kawase et al. in combination with Radke.
Regarding claim 20, Kawase et al. in combination with Radke teach the limitations with respect to claim 17.
However, Kawase et al. in combination with Radke are silent with respect to only a single discharge of a sense node for each of the memory cells.
Tseng et al. teach the circuitry only discharges a sense node a single time [Fig. 6B: step 624, connecting the sense node to the bit line to allow the sense node voltage to discharge into the bit line, para. 109] that is different from the step of performing the sensing operation and comparing the threshold voltages of the memory cells of the selected word line to two reference voltages as taught by Kawase et al.
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Tseng et al. to the teaching of Kawase et al. in combination with Radke such that modifying sensing operation of Kawase et al. in combination with Radke to obtain the comparison between the threshold voltages of the memory cells of the selected word line and two reference voltages using Tseng et al.’s single discharge technique to improve speed and efficiency without changing fundamental operation of Kawase et al. in combination with Radke.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kawase et al. (US 20140063955) in view of Radke (US 20080072120) and Tseng et al. (US 20180374518) as applied to claim 6 above and further in view of Liang et al. (US 20210174880).
Regarding claim 7, Kawase et al. in combination with Radke and Tseng et al. teach the limitations with respect to claim 6.
Furthermore, Tseng et al. disclose wherein the memory device includes sensing circuitry [see Fig. 9, para. 126] with the sense node [see Fig. 9, sense node SEN, para. 127-129].
However, Kawase et al. in combination with Radke and Tseng et al. are silent with respect to wherein a boost voltage can be selectively applied and not applied to the sense node.
Liang et al. teach wherein the memory device includes sensing circuitry [see Fig. 3, para. 25] with the sense node [see Fig. 3, sense node SO, para. 25-26] wherein a boost voltage [a boost driver Vboost configured to provide a boost voltage, para. 25] can be selectively applied and not applied to the sense node [see Fig. 4, at t1-t3, Vboost equal to 0V. At t3, the boost driver Vboost outputs a high voltage vboost1 to start charging the sense node SO, para. 30].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Liang et al. to the teaching of Kawase et al. in combination with Radke and Tseng et al. such that modifying the sensing operation as taught by Kawase et al. in combination with Radke and Tseng et al. to implement a boost voltage applied to the sense node as taught by Liang et al. to achieve more reliable sensing with higher accuracy [see Liang et al.’s para. 5].
Regarding claim 8, Kawase et al. in combination with Radke, Tseng et al. and Liang et al. teach the limitations with respect to claim 7.
Furthermore, Liang et al. disclose wherein the boost voltage is in the range of 0.5±0.3 V [Liang et al. disclose the boost driver Vboost outputs a high voltage vboost1 to start charging the sense node SO, para. 30. It would have been obvious to a person of ordinary skill in the art to choose the boost voltage to be within the claim range (0.5±0.3 V) as a matter of routine design choice].
Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. (US 20210174880) in view of Valeri et al. (US 20200365214) and further in view of Kawase et al. (US 20140063955).
Regarding independent claim 9, Liang et al. disclose a method of reading data of a plurality of memory cells in a selected word line of a memory device, for each of the memory cells [sense circuits are used in flash memory devices to perform a sensing operation (e.g., read and/or verify) on the selected memory cells, para. 25], the method comprising the steps of:
charging a sense node to a charged voltage [see Fig. 4, a precharge current is injected into the sense node SO, para. 26];
discharging the sense node through a selected NAND string for a predetermined time [see Fig. 4, the sense node SO starts to be discharged through memory cell string 310 at t1-t2, para. 30];
sensing a voltage of the sense node after the predetermined time [see Fig. 4, after a certain duration t.sub.a, at time t2, the third switch T3 is turned off as indicated by the signal Vsoblk being set to “off” level. The discharging of the sense node SO stops as the discharging current path is cut off, para. 30];
after sensing the voltage of the sense node, applying a boost voltage to the sense node to boost a residual voltage at the sense node [see Fig. 4, at time t3 the boost driver Vboost outputs a high voltage vboost1 to start charging the sense node SO, para. 30]; and
with the boost voltage being applied to the sense node, sensing the voltage of the sense node again [see Fig. 4, when the voltage at the sense node SO reaches a certain level, sensing a voltage of sense node at t3-t4, para. 30].
However, Liang et al. are silent with respect to compare a threshold voltage of a selected memory cell in the selected NAND string to a first reference voltage at the first sensing of sense node and sensing the voltage of the sense node again without again discharging the sense node through the selected NAND string to compare the threshold voltage of the selected memory cell in the selected NAND string to a second reference voltage at the second sensing of sense node.
Valeri et al. teach discharging the sense node through a selected NAND string [see Fig. 7, at time t4, the data line 204 has discharged, the voltage level of the sense node 640 might be expected to decrease, para. 68];
sensing a voltage of the sense node after the predetermined time [see Fig. 10A-10B, between times t8 and t9, sensing (e.g., a first sensing) can be enabled, or strobed, and the sensing output can indicate a particular level of discharge of sense node 640, para. 85];
after sensing the voltage of the sense node, applying a boost voltage to the sense node to boost a residual voltage at the sense node [see Fig. 10A-10B, at time t10, the boost voltage level of lines 1090 might be increased to the boost voltage level Boost_H, para. 85]; and
with the boost voltage being applied to the sense node, sensing the voltage of the sense node again [see Fig. 10A-10B, between times t11 and t12, sensing (e.g., a second sensing) can be enabled, para. 86] without again discharging the sense node through the selected NAND string [at time t5, the sense node 640 is isolated from the data line 204 before first sensing, para. 69. Valeri et al. do not disclose reopening the path between the first and second sensing stages].
Furthermore, Kawase et al. teach the controller 22 reads data from the NAND flash memory 21 by the upper limit voltage [Fig. 4: step S101] and the lower limit voltage [Fig. 4: step S102] and after that the controller counts, from this read data in step S101 and S102, the number of error cells having threshold voltages between the two threshold voltage distributions in step S103 [para. 61 as well as para. 72-74].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Valeri et al. and Kawase et al. to the teaching of Liang et al. such that modifying Liang et al.’s sensing operation to apply sensing technique of Valeri et al. after Liang et al.’s initial sense node discharge because both references concern NAND sense circuitry using a sense node voltage and capacitive boosting to improve sensing accuracy. This modification would predictably reduce sensing time while retaining multiple sensing determinations. Furthermore, a person having ordinary skill in the art would have been obvious to implement Kawase et al.’s two reference voltage evaluation by performing a first sense node evaluation corresponding to one reference voltage and then, after applying the boost voltage as taught by Liang et al. in combination with Valeri et al. to the sense node, performing a second sense node evaluation corresponding to other reference voltage, thereby doing so would improve sensing margin, reduce error correction processing and increase the reliability of data.
Regarding claim 10, Liang et al. in combination with Valeri et al. and Kawase et al. teach the limitations with respect to claim 9.
Furthermore, Kawase et al. disclose further including the step of: determining that a bit error is present in the data being read in response to a determination that the threshold voltage of the selected memory cell is between the first and second reference voltages [Fig. 9: step 103-104, the controller counts, from this read data in step S101 and S102, the number of error cells having threshold voltages between the two threshold voltage distributions in step S103 and determines whether the number of error cells counted in step S103 is less than or equal to the error specified value set in step S100 (step S104), para. 61 as well as para. 72-74].
Regarding claim 11, Liang et al. in combination with Valeri et al. and Kawase et al. teach the limitations with respect to claim 10.
Furthermore, Kawase et al. disclose further including the step of sending the data being read directly to a user without performing error correction in response to no bit errors being detected [Fig. 9: step S105 and S109, upon determining in step S104 that the number of error cells is less than or equal to the error specified value, the controller 22 copies the page from the copy source to the copy destination (step S105). The controller 22 performs direct copy processing, for example, in the following manner, para. 74-75].
Regarding claim 12, Liang et al. in combination with Valeri et al. and Kawase et al. teach the limitations with respect to claim 11.
Furthermore, Kawase et al. disclose further including the step of sending the data to an error correction code engine prior to sending the data to the user in response to any bit errors being detected [Fig. 9: steps S106-S108, upon determining in step S104 that the number of error cells exceeds the error specified value, the controller 22 reads page data from the NAND flash memory 21 and stores the read page data in the data buffer 27 (step S106). The page data read at the step S106 corresponds to the same page as that indicated by the intra-page addresses set in step S100 and are the entire data of the page instead of partial data corresponding to the intra-page addresses. The ECC circuit 28 then performs error correction of the page data on an ECC frame basis by using the error correction codes contained in the ECC frames (step S107). The ECC circuit 28 stores the corrected page data in the data buffer 27 upon removing the error correction codes, para. 76. The data buffer 27 temporarily stores a predetermined amount of data when transmitting data read from the NAND flash memory 21 to the host device 10, para. 35].
Regarding claim 13, Liang et al. in combination with Valeri et al. and Kawase et al. teach the limitations with respect to claim 9.
Furthermore, Kawase et al. disclose wherein the data is in a single bit per memory cell (SLC) storage format [para. 63 as well as para. 86].
Regarding claim 14, Liang et al. in combination with Valeri et al. and Kawase et al. teach the limitations with respect to claim 9.
Furthermore, Liang et al. disclose wherein the boost voltage is in the range of 0.5±0.3 V [Liang et al. disclose the boost driver Vboost outputs a high voltage vboost1 to start charging the sense node SO, para. 30. It would have been obvious to a person of ordinary skill in the art to choose the boost voltage to be within the claim range (0.5±0.3 V) as a matter of routine design choice].
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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