DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (JP2024-004046 Japan 01/15/2024).
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 06/14/2024, 02/11/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 06/14/2024. These drawings are review and accepted by the examiner.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it uses the phrase “comprising” in page 1, line 1, which is implied. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 1-19’s “control circuit”; “circuitry” that is “configured to” perform recited operations;
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US 10,409,499 B2) in view of Kim (US 7,511,996 B2).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Kimura, for example in Figs. 1-16, discloses a semiconductor memory device (see for example in Fig. 1 related in Figs. 2-16) comprising: a first memory string (e.g., 16; in Fig. 3 related in Figs. 1-2, 4-16) in which a plurality of memory cells (e.g., MTs; in Fig. 3 related in Figs. 1-2, 4-16) including a first memory cell and a second memory cell are connected in series (within 16; in Fig. 3 related in Figs. 1-2, 4-16); a first word line connected to a gate of the first memory cell (e.g., WL; in Fig. 3 related in Figs. 1-2, 4-16); a second word line connected to a gate of the second memory cell (e.g., WL; in Fig. 3 related in Figs. 1-2, 4-16); a first bit line connected to a first end of the first memory string (e.g., BL; in Fig. 3 related in Figs. 1-2, 4-16); a source line connected to a second end of the first memory string (e.g., SL; in Fig. 3 related in Figs. 1-2, 4-16); and control circuitry (e.g., 14; in Fig. 2 related in Figs. 1, 3-16) configured to, in performing a program operation on the first memory cell (see for example in Figs. 8-10 related in Figs. 1-7, 11-16) place a channel of the first memory string into a floating state (e.g., Floating; in Figs. 10, 13 related in Figs. 1-9, 11-12, 14-16) in which the channel is electrically insulated from the first bit line and the source line (e.g., SGD or VSD2 and SGS or VSS are turn off; in Figs. 10, 13 related in Figs. 1-9, 11-12, 14-16) while applying a write voltage to the first word line (e.g., VPGM to selected WL; in Fig. 10, 12-13 related in Figs. 1-9, 11, 14-16); and decrease a voltage of the second word line (e.g., non-selected WL; in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16) from a first voltage (e.g., VPASS; in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16) that is less than the write voltage (e.g., VPGM; in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16) to a second voltage after placing the channel of the first memory string into the floating state (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16).
However, Kimura is silent with regard to the second voltage that is less than the first voltage.
In the same field of endeavor, Kim, for example in Figs. 1-16, discloses the second voltage that is less than the first voltage (e.g., VPASS or V3 less than V2; in Fig. 14 related in Figs. 1-13, 15-16).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Kimura such as NAND flash memory device and system including SLC and MLC write modes (see for example in Figs. 1-16 of Kimura) by incorporating the teaching of Kim such as flash memory program inhibit scheme (see for example in Figs. 1-16 of Kim), for the purpose of controlling the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming (Kim, see abstract).
For apparatus claims 1-19, MPEP 2112.01(I) instructs examiners, “When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed inherent.” Kimura and Kim disclose a substantially identical memory apparatus; the recited functions are presumed inherent. See also, MPEP Foreword (“[T]he Manual contains instructions to examiners, as well as other material in the nature of information and interpretation, and outlines the current procedures which the examiners are required or authorized to follow in appropriate cases in the normal examination of a patent application.”).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicants are reminded that argument of counsel is not evidence (see MPEP 2145(I)). Applicants are reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 2, the above Kimura/Kim, the combination discloses wherein the control circuitry decreases the voltage of the second word line to the second voltage to decrease a voltage of the channel of the first memory string to be less than a ground voltage (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 3, the above Kimura/Kim, the combination discloses further comprising: a first selection transistor provided between the first bit line and a first end of the plurality of memory cells (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 4, the above Kimura/Kim, the combination discloses further comprising: a second selection transistor provided between the source line and a second end of the plurality of memory cells (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 5, the above Kimura/Kim, the combination discloses wherein the control circuitry is configured to, in performing a program operation on the first memory cell, place the first memory string into the floating state by placing the first selection transistor and the second selection transistor into an OFF state (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 6, the above Kimura/Kim, the combination discloses further comprising: a second memory string in which a plurality of memory cells including a third memory cell and a fourth memory cell are connected in series; and a second bit line connected to a first end of the second memory string (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 7, the above Kimura/Kim, the combination discloses wherein the first word line is connected to a gate of the third memory cell, the second word line is connected to a gate of the fourth memory cell, and the source line is connected to a second end of the second memory string (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 8, the above Kimura/Kim, the combination discloses the control circuitry is configured to, in performing a program operation on the first memory cell, decrease a voltage of the second word line from the first voltage to the second voltage while placing a channel of the second memory string into the floating state (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 9, the above Kimura/Kim, the combination discloses wherein a voltage of the channel of the second memory string becomes less than the first voltage when the control circuitry decreases the voltage of the second word line to the second voltage (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 10, the above Kimura/Kim, the combination discloses wherein a threshold voltage of the first selection transistor and a threshold voltage of the second selection transistor are higher than a threshold voltage of the plurality of memory cells in an erasure state (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 11, the above Kimura/Kim, the combination discloses further comprising: a first gate line connected to a gate of the first selection transistor (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 12, the above Kimura/Kim, the combination discloses wherein the control circuitry is configured to, in performing a program operation on the first memory cell (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above), make a voltage of the first gate line less than a ground voltage when the control circuitry places the first memory string into the floating state (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding Independent Claim 13, Kimura, for example in Figs. 1-16, discloses a semiconductor memory device (see for example in Fig. 1 related in Figs. 2-16) comprising: circuitry (e.g., 14; in Fig. 2 related in Figs. 1, 3-16) configured to perform control to cause a channel of a first memory string (e.g., 16; in Fig. 3 related in Figs. 1-2, 4-16) including a first memory cell and a second memory cell connected in series (e.g., memory cell within 16; in Fig. 3 related in Figs. 1-2, 4-16) to be in a floating state (e.g., Floating; in Figs. 10, 13 related in Figs. 1-9, 11-12, 14-16) in which the channel is electrically insulated (e.g., SGD or VSD2 and SGS or VSS are turn off; in Figs. 10, 13 related in Figs. 1-9, 11-12, 14-16) from a first bit line connected to a first end of the first memory string (e.g., BL; in Fig. 3 related in Figs. 1-2, 4-16) and a source line connected to a second end of the first memory string (e.g., SL; in Fig. 3 related in Figs. 1-2, 4-16) while applying a write voltage to a first word line connected to a gate of the first memory cell (e.g., VPGM to selected WL; in Fig. 10, 12-13 related in Figs. 1-9, 11, 14-16); and decrease a voltage of a second word line connected to a gate of the second memory cell (e.g., VPASS; in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16) from a first voltage that is less than the write voltage to a second voltage after placing the channel of the first memory string into the floating state (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16).
However, Kimura is silent with regard to the second voltage that is less than the first voltage.
In the same field of endeavor, Kim, for example in Figs. 1-16, discloses the second voltage that is less than the first voltage (e.g., VPASS or V3 less than V2; in Fig. 14 related in Figs. 1-13, 15-16).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Kimura such as NAND flash memory device and system including SLC and MLC write modes (see for example in Figs. 1-16 of Kimura) by incorporating the teaching of Kim such as flash memory program inhibit scheme (see for example in Figs. 1-16 of Kim), for the purpose of controlling the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming (Kim, see abstract).
Regarding claim 14, the above Kimura/Kim, the combination discloses wherein a voltage of the channel of the first memory string becomes less than a ground voltage when the circuitry decreases the voltage of the second word line to the second voltage (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 15, the above Kimura/Kim, the combination discloses wherein the circuitry is configured to perform control to cause the first memory strong to be in the floating state by controlling a first selection transistor and a second selection transistor to be in an OFF state (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 16, the above Kimura/Kim, the combination discloses wherein the first selection transistor is between the first bit line and a first end of the first memory string, and the second selection transistor is between the source line and a second end of the first memory string (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 17, the above Kimura/Kim, the combination discloses wherein a threshold voltage of the first selection transistor and a threshold voltage of the second selection transistor are higher than a threshold voltage of the plurality of memory cells in an erasure state (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 18, the above Kimura/Kim, the combination discloses wherein the circuitry is configured to perform control to decrease a voltage of a second word line of a second memory string from the first voltage to the second voltage while placing a channel of the second memory string into the floating state (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding claim 19, the above Kimura/Kim, the combination discloses wherein the circuity includes a central processing unit (CPU) configured to perform control to program a memory cell array (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16 of Kimura and also see in Fig. 14 related in Figs. 1-13, 15-16 of Kim, as discussed above).
Regarding Independent Claim 20, Kimura, for example in Figs. 1-16, discloses a method performed (see for example in Figs. 7, 11, 14, 16 related in Figs. 1-6, 8-10, 12-13, 15) by a semiconductor memory device (see for example in Fig. 1 related in Figs. 2-16) applying a write voltage to a word line of a memory cell array (e.g., VPGM; in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16), the method comprising: causing a channel of a first memory string (e.g., 16; in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16) including a first memory cell and a second memory cell connected in series (within 16; in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16) to be in a floating state (e.g., Floating; in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16) in which the channel is electrically insulated from a first bit line (e.g., BL; in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16) connected to a first end of the first memory string (e.g., BL; in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16) and a source line connected to a second end of the first memory string (e.g., SL; in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16); and decreasing a voltage of a second word line connected to a gate of the second memory cell (e.g., VPASS; in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16) from a first voltage that is less than the write voltage to a second voltage after placing the channel of the first memory string into the floating state (see for example in Figs. 10, 12-13 related in Figs. 1-9, 11, 14-16).
However, Kimura is silent with regard to the second voltage that is less than the first voltage.
In the same field of endeavor, Kim, for example in Figs. 1-16, discloses the second voltage that is less than the first voltage (e.g., VPASS or V3 less than V2; in Fig. 14 related in Figs. 1-13, 15-16).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Kimura such as NAND flash memory device and system including SLC and MLC write modes (see for example in Figs. 1-16 of Kimura) by incorporating the teaching of Kim such as flash memory program inhibit scheme (see for example in Figs. 1-16 of Kim), for the purpose of controlling the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming (Kim, see abstract).
Applicant are reminded that when presenting amendments to claims. In order to be fully responsive, an attempt should be made to point out the patentable novelty (see MPEP 714.04). Additionally, Applicant should point out where and/or how the originally filed disclosure supports the amendment(s) (see MPEP 2163 (II)(A)).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 11/29/2025